参数资料
型号: LTC1624CS8#PBF
厂商: Linear Technology
文件页数: 20/28页
文件大小: 0K
描述: IC REG CTRLR BST FLYBK INV 8SOIC
标准包装: 100
PWM 型: 电流模式
输出数: 1
频率 - 最大: 225kHz
占空比: 95%
电源电压: 3.5 V ~ 36 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 管件
产品目录页面: 1333 (CN2011-ZH PDF)
LTC1624
APPLICATIO N S I N FOR M ATIO N
Positive-to-negative converters have high ripple current in
both the input and output capacitors. For long capacitor
lifetime, the RMS value of this current must be less than
the high frequency ripple rating of the capacitor.
The following formula gives an approximate value for RMS
ripple current. This formula assumes continuous mode
and low current ripple. Small inductors will give somewhat
higher ripple current, especially in discontinuous mode.
For the exact formulas refer to Application Note 44, pages
28 to 30. The input and output capacitor ripple current
(occurring at V IN(MIN) ) is:
I TH /RUN pin below 0.8V relative to the LTC1624 ground
pin. With the LTC1624 ground pin referenced to – V OUT ,
the nonimal range on the I TH /RUN pin is – V OUT (in
shutdown) to (– V OUT + 2.4V)(at Max I OUT ). Referring to
Figure 15, M2, M3 and R3 provide a level shift from typical
TTL levels to the LTC1624 operating as positive-to-nega-
tive converter. MOSFET M3 supplies gate drive to M2
during shutdown, while M2 pulls the I TH/RUN pin voltage to
– V OUT , shutting down the LTC1624.
Step-Down Converters: PC Board Layout Checklist
When laying out the printed circuit board, the following
Capacitor I RMS = ( ff )( I OUT )
V OUT
V IN
checklist should be used to ensure proper operation of the
LTC1624. These items are also illustrated graphically in
the layout diagram of Figure 9. Check the following in your
layout:
ff = Fudge factor (1.2 to 2.0)
The output peak-to-peak ripple voltage is:
V OUT(P-P) = R ESR (I D(MAX) )
The input capacitor can also see a very high surge current
when a battery is suddenly connected, and solid tantalum
capacitors can fail under this condition. Be sure to specify
surge tested capacitors.
Positive-to-Negative Converter: Duty Cycle
Limitations
The minimum on-time of 450ns sets a limit on how high
of input-to-output ratio can be tolerated while not skipping
cycles. This only impacts designs when very low output
voltages ( ? V OUT ? < 2.5V) are needed. The maximum input
voltage is:
1. Are the signal and power grounds segregated? The
LTC1624 ground (Pin 4) must return to the (–) plate
of C OUT.
2. Does the V FB (Pin 3) connect directly to the feedback
resistors? The resistive divider R1, R2 must be con-
nected between the (+) plate of C OUT and signal ground.
The 100pF capacitor should be as close as possible to
the LTC1624.
3. Does the V IN lead connect to the input voltage at the
same point as R SENSE and are the SENSE – and V IN leads
routed together with minimum PC trace spacing? The
filter capacitor between V IN and SENSE – should be as
close as possible to the LTC1624.
4. Does the (+) plate of C IN connect to R SENSE as closely
as possible? This capacitor provides the AC current to
V IN(MAX) < 10.1V OUT + 5V
For DC > 9%
the MOSFET(s). Also, does C IN connect as close as
possible to the V IN and ground pin of the LTC1624?
V IN(MAX) < 36V – ? V OUT ? For absolute maximum ratings
Positive-to-Negative Converter: Shutdown
Considerations
Since the ground pin on the LTC1624 is referenced to
– V OUT , additional circuitry is needed to put the LTC1624
into shutdown. Shutdown is enabled by pulling the
20
This capacitor also supplies the energy required to
recharge the bootstrap capacitor. Adequate input
decoupling is critical for proper operation.
5. Keep the switch node SW away from sensitive small-
signal nodes. Ideally, M1, L1 and D1 should be con-
nected as closely as possible at the switch node.
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