参数资料
| 型号： | LTC1657LIN |
| 厂商： | Linear Technology |
| 文件页数： | 2/16页 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT R-R MICROPWR 28DIP |
| 标准包装： | 47 |
| 设置时间： | 20µs |
| 位数： | 16 |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 3.25mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 28-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 28-PDIP |
| 包装： | 管件 |
| 输出数目和类型： | 1 电压，单极；1 电压，双极 |
| 采样率（每秒）： | * |
10
LTC1657/LTC1657L
Parallel Interface
The data on the input of the DAC is written into the DAC’s
input registers when Chip Select (CSLSB and/or CSMSB)
and WR are at a logic low. The data that is written into the
input registers will depend on which of the Chip Selects
are at a logic low (see Digital Interface Truth Table). If WR
and CSLSB are both low and CSMSB is high, then only
data on the eight LSBs (D0 to D7) is written into the input
registers. Similarly, if WR and CSMSB are both low and
CSLSB is high, then only data on the eight MSBs (D8 to
D15) is written into the input registers. Data is written into
both the Least Significant Data Bits (D0 to D7) and the Most
Significant Bits (D8 to D15) at the same time if WR, CSLSB
and CSMSB are low. If WR is high or both CSMSB and
CSLSB are high, then no data is written into the input
registers.
Once data is written into the input registers, it can be
written into the DAC register. This will update the analog
voltage output of the DAC. The DAC register is written by
a logic low on LDAC. The data in the DAC register will be
held when LDAC is high.
When WR, CSLSB, CSMSB and LDAC are all low, the
registers are transparent and data on pins D0 to D15 flows
directly into the DAC register.
For an 8-bit data bus connection, tie the MSB byte data
pins to their corresponding LSB byte pins (D15 to D7, D14
to D6, etc).
Power-On Reset
The LTC1657/LTC1657L have an internal power-on reset
that resets all internal registers to 0’s on power-up and
VOUT pin forces to GND (equivalent to the CLR pin
function).
Reference
The LTC1657/LTC1657L include an internal 2.048V/1.25V
reference, giving the LTC1657/LTC1657L a full-scale range
of 4.096V/2.5V in the gain-of-2 configuration. The onboard
reference in the LTC1657/LTC1657L is not internally
connected to the DAC’s reference resistor string but is
provided on an adjacent pin for flexibility. Because the
internal reference is not internally connected to the DAC
resistor ladder, an external reference can be used or the
resistor ladder can be driven by an external source in
multiplying applications. The external reference or source
must be capable of driving the 16k (minimum) DAC ladder
resistance.
Internal reference output noise can be reduced with a
bypass capacitor to ground. (Note: The reference does not
require a bypass capacitor to ground for nominal opera-
tion.) When bypassing the reference, a small value resis-
tor in series with the capacitor is recommended to help
reduce peaking on the output. A 10
resistor in series
with a 4.7
F capacitor is optimum for reducing reference
generated noise. Internal reference output voltage noise
spectral density at 1kHz is typically 150nV/
√Hz(LTC1657),
90nV/
√Hz (LTC1657L)
DAC Resistor Ladder
The high and low end of the DAC ladder resistor string
(REFHI and REFLO, respectively) are not connected inter-
nally on this part. Typically, REFHI will be connected to
REFOUT and REFLO will be connected to GND. X1/X2
connected to GND will give the LTC1657/LTC1657L a full-
scale output swing of 4.096V/2.5V.
Either of these pins can be driven up to VCC – 1.5V when
using the buffer in the gain-of-1 configuration. The resistor
string pins can be driven to VCC/2 when the buffer is in the
gain of 2 configuration. The resistance between these two
pins is typically 25k (16k min) (LTC1657), 23k (16k min)
(LTC1657L).
Voltage Output
The output buffer for the LTC1657/LTC1657L can be
configured for two different gain settings. By tying the
X1/X2 pin to GND, the gain is set to 2. By tying the X1/X2
pin to VOUT, the gain is set to unity.
The LTC1657/LTC1657L rail-to-rail buffered output can
source or sink 5mA within 500mV of the positive supply
voltage or ground at room temperature. The output stage
is equipped with a deglitcher that results in a midscale
glitch impulse of 8nV s. The output swings to within a few
millivolts of either supply rail when unloaded and has an
equivalent output resistance of 40
(LTC1657), 120
(LTC1657L) when driving a load to the rails.
OPERATIO
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