参数资料
| 型号： | LTC1661CMS8 |
| 厂商： | Linear Technology |
| 文件页数： | 13/14页 |
| 文件大小： | 0K |
| 描述： | IC D/A CONV 10BIT MICRPWR 8-MSOP |
| 标准包装： | 50 |
| 设置时间： | 30µs |
| 位数： | 10 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 260µW |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 管件 |
| 输出数目和类型： | 2 电压，单极 |
| 采样率（每秒）： | * |
LTC1661
8
1661fa
OPERATION
Transfer Function
The transfer function for the LTC1661 is:
VOUT(DEAL) =
k
1024
VREF
where k is the decimal equivalent of the binary DAC input
code D9-D0 and VREF is the voltage at REF (Pin 6).
Power-On Reset
The LTC1661 positively clears the outputs to zero scale
when power is first applied, making system initialization
consistent and repeatable.
Power Supply Sequencing
The voltage at REF (Pin 4) must not ever exceed the
voltage at VCC (Pin 6) by more than 0.3V. Particular care
should be taken in the power supply turn-on and turn-
off sequences to assure that this limit is observed. See
Absolute Maximum Ratings.
Serial Interface
See Table 1. The 16-bit Input word consists of the 4-bit
Controlcode,the10-bitInputcodeandtwodon’t-carebits.
Table 1. LTC1661 Input Word
A3 A2 A1
CONTROL CODE
A0 D9 D8 D7 D6 D5 D4 D3 D2 D1
X1 X0
D0
INPUT CODE
INPUT WORD
DON’T
CARE
After the Input word is loaded into the register (see
Figure1), it is internally converted from serial to parallel
format. The parallel 10-bit-wide input code data path is
then buffered by two latch registers.
The first of these, the input register, is used for loading
new input codes. The second buffer, the DAC register, is
used for updating the DAC outputs. Each DAC has its own
10-bit input register and 10-bit DAC register.
Byselectingtheappropriate4-bitcontrolcode(seeTable2)
it is possible to perform single operations, such as loading
one DAC or changing power-down status (sleep/wake).
In addition, some Control codes perform two or more
operations at the same time. For example, one such code
loads DAC A, updates both outputs and wakes the part
up. The DACs can be loaded separately or together, but
the outputs are always updated together.
Register Loading Sequence
See Figure 1. With CS/LD held low, data on the DIN input
is shifted into the 16-bit shift register on the positive edge
of SCK. The 4-bit control code, A3-A0, is loaded first, then
the10-bitInputcode,D9-D0,orderedMSB-to-LSBineach
case. Two don’t-care bits, X1 and X0, are loaded last. When
the full 16-bit Input word has been shifted in, CS/LD is
pulled high, causing the system to respond according to
Table2. The clock is disabled internally when CS/LD is
high. Note: SCK must be low when CS/LD is pulled low.
Sleep Mode
DAC control code 1110b is reserved for the special sleep
instruction (see Table 2). In this mode, the digital parts
of the circuit stay active while the analog sections are
disabled; static power consumption is greatly reduced.
The reference input and analog outputs are set in a high
impedance state and all DAC settings are retained in
memory so that when Sleep mode is exited, the outputs
of DACs not updated by the wake command are restored
to their last active state.
Sleep mode is initiated by performing a load sequence
using control code 1110b (the DAC input code D9-D0 is
ignored).
To save instruction cycles, the DACs may be prepared
with new input codes during Sleep (control codes 0001b
and 0010b); then, a single command (1000b) can be used
both to wake the part and to update the output values.
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