参数资料
型号: LTC1661IMS8#TRPBF
厂商: Linear Technology
文件页数: 2/14页
文件大小: 0K
描述: IC D/A CONV 10BIT MICRPWR 8-MSOP
标准包装: 2,500
设置时间: 30µs
位数: 10
数据接口: 串行
转换器数目: 2
电压电源: 单电源
功率耗散(最大): 260µW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-MSOP
包装: 带卷 (TR)
输出数目和类型: 2 电压,单极
采样率(每秒): *
LTC1661
10
1661fa
OPERATION
Voltage Outputs
Each of the rail-to-rail output amplifiers contained in the
LTC1661 can typically source or sink up to 5mA (VCC=5V).
Theoutputsswingtowithinafewmillivoltsofeithersupply
whenunloadedandhaveanequivalentoutputresistanceof
85Ω (typical) when driving a load to the rails. The output
amplifiers are stable driving capacitive loads up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. A 1F
load can be successfully driven by inserting a 20Ω resis-
tor in series with the VOUT pin. A 2.2F load needs only a
10Ω resistor, and a 10F electrolytic capacitor can be used
withoutanyresistor(theequivalentseriesresistanceofthe
capacitor itself provides the required small resistance). In
anyofthesecases,largervaluesofresistance,capacitance
or both may be substituted for the values given.
Rail-to-Rail Output Considerations
In any rail-to-rail DAC, the output swing is limited to volt-
ages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 2b.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC. If VREF = VCC and the DAC full-scale
error (FSE) is positive, the output for the highest codes
limits at VCC as shown in Figure 2c. No full-scale limiting
can occur if VREF is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
1661 F02
INPUT CODE
(2b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
512
0
1023
INPUT CODE
OUTPUT
VOLTAGE
(2a)
VREF = VCC
(2c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (2a) Overall Transfer Function (2b) Effect of Negative
Offset for Codes Near Zero Scale (2c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
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