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参数资料
| 型号： | LTC1663IMS8#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 11/12页 |
| 文件大小： | 0K |
| 描述： | IC D/A CONV 10BIT R-R 8-MSOP |
| 标准包装： | 2,500 |
| 设置时间： | 30µs |
| 位数： | 10 |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 630µW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 1 电压，单极 |
| 采样率（每秒）： | * |
LTC1663
8
1663fd
APPLICATIONS INFORMATION
Bit (Wr) = 0. The LTC1663 acknowledges and the master
delivers the command byte. The LTC1663 acknowledges
and latches the command byte into the command byte
input register. The master then delivers the least signicant
data byte. Again the LTC1663 acknowledges and the data
is latched into the least signicant data byte input register.
The master then delivers the most signicant data byte.
The LTC1663 acknowledges once more and latches the
data into the most signicant data byte input register.
Lastly, the master terminates the communication with a
STOP condition. On the reception of the STOP condition,
the LTC1663 transfers the input register information to
output registers and the DAC output is updated.
Slave Address (MSOP Package Only)
The LTC1663 can respond to one of eight 7-bit addresses.
The rst 4 bits (MSBs) have been factory programmed to
0100. The rst 4 bits of the LTC1663-8 have been factory
programmed to 0011. The three address bits, AD2, AD1
and AD0 are programmed by the user and determine the
LSBs of the slave address, as shown in the table below:
LTC1663
LTC1663-8
AD2
AD1
AD0
0100 xxx
0011 xxx
L
0100 000
0011 000
L
H
0100 001
0011 001
L
H
L
0100 010
0011 010
L
H
0100 011
0011 011
H
L
0100 100
0011 100
H
L
H
0100 101
0011 101
H
L
0100 110
0011 110
H
0100 111
0011 111
Slave Address (SOT-23 Package)
The slave address for the SOT-23 package has been
factory programmed to be “0100 000” (LTC1663),
“0100 001” (LTC1663-1) and “0100 010” (LTC1663-2) If
another address is required, please consult the factory.
Command Byte
7
6543
2
1
0
X
XXXX
BG
SD
SY
1
0
Allows update on Acknowledge of SYNC Address only
Update on Stop condition only (Power-On Default)
SD
1
0
Puts the device in power-down mode
Puts the device in standard operating mode
(Power-On Default)
BG
1
0
Selects the internal bandgap reference
Selects the supply as the reference (Power-On Default)
X
Don’t Care
The stop condition normally initiates the update of the
DAC’s output latches. Simultaneous update of more than
one DAC or other devices on the bus can be achieved by
reissuing new start bit, address, command and data bytes
before issuing a nal stop condition (which will update
all the devices). An alternate way to achieve simultaneous
LTC1663 updates is to override the stop condition update
by setting the “SY” bit of the command byte. Setting this
bit sets the device to update the DAC output latches only
at the reception of a SYNC address quick command. The
actual update occurs on the rising edge of SCL during the
Acknowledge. In this way, all devices can update on the
reception of the SYNC address quick command instead
of the STOP condition.
A Shutdown (SD) bit = HIGH will put the device in a low
power state but retain all data latch information. Shutdown
will occur at the reception of a STOP condition. This way
shutdown could be synchronized to other devices. The
output impedance of the DAC will go to a high impedance
state (≈ 500kΩ to GND).
The Bandgap (BG) bit when set to “0” selects the DAC
supply voltage as its voltage reference. The full-scale
output of the DAC with this setting is equal to the supply
voltage. When the BG bit is set to “1,” the internal bandgap
reference (≈1.25V) is selected as the DAC’s reference. The
full-scale output voltage for this setting is 2.5V.
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