参数资料
| 型号： | LTC1664IN |
| 厂商： | Linear Technology |
| 文件页数： | 15/16页 |
| 文件大小： | 0K |
| 描述： | IC DAC 10BIT QUAD MICRPWR 16DIP |
| 标准包装： | 25 |
| 设置时间： | 6µs |
| 位数： | 10 |
| 数据接口： | 串行 |
| 转换器数目： | 4 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 1mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 16-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 16-PDIP |
| 包装： | 管件 |
| 输出数目和类型： | 4 电压，单极；4 电压，双极 |
| 采样率（每秒）： | * |
LTC1664
8
1664fa
operation
Transfer Function
The transfer function is
VOUT(IDEAL) =
k
1024
VREF
where k is the decimal equivalent of the binary DAC input
code and VREF is the voltage at REF (Pin 6).
Power-On Reset
The LTC1664 clears the outputs to zero-scale when power
is first applied, making system initialization consistent
and repeatable.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
–0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Rat-
ings). Particular care should be taken to observe these
limitsduringpowersupplyturn-onandturn-offsequences,
when the voltage at VCC (Pin 16) is in transition. If it is
not possible to sequence the supplies, connect a Schottky
diode from REF (anode) to VCC (cathode).
Serial Interface
Referring to Figure 2: With CS/LD held low, data on the DIN
input is shifted into the 16-bit shift register on the positive
edge of SCK. The 4-bit DAC address, A3-A0, is loaded first
(see Table 2), then the 10-bit input code, D9-D0, ordered
MSB-to-LSB in each case. Two don’t-care bits, X1-X0,
are loaded last. When the full 16-bit input word has been
shifted in, CS/LD is pulled high, loading the DAC register
with the word and causing the addressed DAC output(s)
to update. The clock is disabled internally when CS/LD is
high. Note: SCK must be low before CS/LD is pulled low.
The buffered serial output of the shift register is avail-
able on the DOUT pin, which swings from GND to VCC.
Data appears on DOUT 16 positive SCK edges after being
applied to DIN.
Multiple LTC1664’s can be controlled from a single 3-wire
serial port (i.e., SCK, DINandCS/LD)byusingtheincluded
daisychain facility. A series of m chips is configured by
connecting each DOUT (except the last) to DIN of the next
chip, forming a single 16m-bit shift register. The SCK and
CS/LD signals are common to all chips in the chain. In
use, CS/LD is held low while m 16-bit words are clocked
to DIN of the first chip; CS/LD is then pulled high, updating
all of them simultaneously.
Sleep Mode
DACaddress1110bisreservedforthespecialsleepinstruc-
tion (see Table 2). In this mode, the digital interface stays
active while the analog circuits are disabled; static power
consumption is thus virtually eliminated. The reference
input and analog outputs are set in a high impedance state
and all DAC settings are retained in memory so that when
sleep mode is exited, the outputs of DACs not updated by
the Wake command are restored to their last active state.
Sleep mode is initiated by performing a load sequence to
address 1110b (the DAC input word D9-D0 is ignored).
Once in sleep mode, a load sequence to any other ad-
dress (including “No Change” address 0000b) causes
the LTC1664 to Wake. It is possible to keep one or more
chips of a daisy chain in continuous sleep mode by giving
the sleep instruction to these chips each time the active
chips in the chain are updated.
Voltage Outputs
Each of the four rail-to-rail output amplifiers contained in
the LTC1664 can source or sink up to 5mA. The outputs
swing to within a few millivolts of either supply rail when
unloaded and have an equivalent output resistance of 85Ω
when driving a load to the rails. The output amplifiers are
stable driving capacitive loads of up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. A 1F
A3 A2 A1
ADDRESS/CONTROL
A0 D9 D8 D7 D6 D5 D4 D3 D2 D1
X1 X0
D0
INPUT CODE
Table 1. LTC1664 Input Word
DON’T CARE
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