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参数资料
| 型号： | LTC1734ES6#TR-4.1 |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | BATTERY CHARGE CONTROLLER, PDSO6 |
| 封装： | PLASTIC, SOT-23, 6 PIN |
| 文件页数： | 7/8页 |
| 文件大小： | 140K |
| 代理商： | LTC1734ES6#TR-4.1 |
7
LTC1734
APPLICATIONS INFORMATION
WU
U
For example, to program a charge current of 500mA with
a minimum supply voltage of 4.75V, the minimum operat-
ing VCE is:
VCE(MIN)(V) = 4.75 – (0.5)(0.1) – 4.2 = 0.5V
The actual battery charge current (IBAT) is slightly smaller
than the expected charge current because the charger
senses the emitter current and the battery charge current
will be reduced by the base current. In terms of
β (IC/IB),
IBAT can be calculated as follows:
IBAT(A) = 1000 IPROG[β/(β + 1)]
If
β = 50, then IBAT is 2% low. If desired, the 2% loss can
be compensated for by increasing IPROG by 2%.
Another important factor to consider when choosing the
PNP pass transistor is the power handling capability. The
PNP’s data sheet will usually give the maximum rated
power dissipation at a given ambient temperature with a
power derating for elevated temperature operation. The
maximum power dissipation of the PNP when charging is:
PD(MAX)(W) = IBAT (VDD(MAX) – VBAT(MIN))
VDD(MAX) is the maximum supply voltage and VBAT(MIN) is
the minimum battery voltage when discharged.
(>300) and very low ESR output capacitors (especially
ceramic) reduces the phase margin, possibly resulting in
oscillation. Adding series resistance to the capacitor will
restore the phase margin. The last transistor listed in each
row of Table 1 is high beta.
In the constant current mode it is the PROG pin that is in
the feedback loop and not the battery. Because the PROG
pin is in a closed-loop signal path, the pole frequency
should be kept above 400kHz to maintain adequate AC
stability. In addition, high loop gains should be avoided by
limiting RPROG to 15k or less. The pole frequency is
determined by RPROG and the external capacitive loading
on the PROG pin. Once RPROG is determined, the maxi-
mum value of C which will give adequate stability can be
calculated as follows:
CMAX (F) = 1/(6.28 RPROG 400k)
A capacitance of 25pF or less is acceptable for any RPROG
value.
To minimize capacitive loading of the PROG pin, a 10k
resistor can be added between the PROG pin and the
monitoring circuit to allow the charger to be unaffected by
the capacitance.
VCC Bypass Capacitor
Many types of capacitors with values ranging from 1
F to
10
F located close to the LTC1734 will provide adequate
input bypassing. However, caution must be exercised
when using multilayer ceramic capacitors. Because of the
self resonant and high Q characteristics of some types of
ceramic capacitors, high voltage transients can be gener-
ated under some start-up conditions, such as connecting
the charger input to a hot power source. To prevent these
transients from exceeding the absolute maximum voltage
rating, several ohms can be added in series with the input
ceramic capacitor.
Internal Protection
Internal protection is provided to prevent excessive DRIVE
currents (IDSHRT) and excessive internal self-heating in
case of a fault condition, such as a shorted DRIVE pin or
the external PNP pass transistor operating in deep
saturation.
Table 1. Recommended Low VCESAT PNP Transistors
Maximum
Maximum PD at
Package
Current (A)
TA = 25°C
Style
Zetex Part Number
1
0.5
SOT-23
FMMT549 or FMMT717
1
SOT-89
FCX589 or FCX717
2
SOT-223
FZT549 or BCP69
Stability
The LTC1734 contains two control loops; constant voltage
and constant current. To maintain adequate AC stability in
the constant voltage mode, a capacitance (5
F to 100F)
is required from the BAT pin to ground. A battery and the
interconnecting wires can appear inductive at high fre-
quencies, and since the battery is in the feedback loop, this
capacitance is necessary to compensate for the induc-
tance. The capacitor ESR can range from near zero ohms
to several ohms.
In general, compensation is optimal with 4.7
F to 22F
and ESR of 0.5
to 1.5. Using high beta PNP transistors
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