参数资料
型号: LTC1735CS-1#PBF
厂商: Linear Technology
文件页数: 11/28页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 16-SOIC
标准包装: 50
PWM 型: 电流模式
输出数: 1
频率 - 最大: 335kHz
占空比: 99.4%
电源电压: 3.5 V ~ 30 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 85°C
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
包装: 管件
LTC1735-1
APPLICATIO S I FOR ATIO
? 1 . 61 ( 10 7 ) ?
? I L =
V OUT ? 1 – OUT ?
? V IN ?
ThevalueofC OSC iscalculatedfromthedesiredoperating
frequency assuming no external clock input on the PGOOD
pin:
C OSC ( pF ) = ? ? – 11
? ? Frequency ? ?
A graph for selecting C OSC versus frequency is given in
Figure 2. The maximum recommended switching fre-
quency is 550kHz .
The internal oscillator runs at its nominal frequency (f O )
when the PGOOD pin is pulled high (to INTV CC ) though a
series resistor or connected to ground. Clocking the
PGOOD pin above and below 1.2V will cause the internal
oscillator to injection-lock to an external clock signal
applied to the PGOOD pin with a frequency between 0.9f O
and 1.3f O . The clock high level must exceed 1.3V for at
least 0.3 μ s, and the clock low level must be less than 0.3V
for at least 0.3 μ s. The top MOSFET turn-on will synchro-
nize with the rising edge of the external clock.
Attempting to synchronize to too high of an external
frequency (above 1.3f O ) can result in inadequate slope
compensation and possible loop instability at high duty
cycles. If this condition exists, simply lower the value of
C OSC so (f EXT = f O ) according to Figure 2.
100.0
87.5
75.0
62.5
50.0
37.5
25.0
12.5
clamp present in Burst Mode operation is removed,
providing constant frequency discontinuous operation
over the widest possible output current range. In this
mode the synchronous MOSFET is forced on once every
10 clock cycles to recharge the bootstrap capacitor. This
minimizes audible noise while maintaining reasonably
high efficiency.
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge losses. In addition to this basic trade
off, the effect of inductor value on ripple current and low
current operation must also be considered.
The inductor value has a direct effect on ripple current. The
inductor ripple current ? I L decreases with higher induc-
tance or frequency and increases with higher V IN or V OUT :
1 ? V ?
( f )( L )
Accepting larger values of ? I L allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ? I L = 0.3 to 0.4(I MAX ). Remember,
the maximum ? I L occurs at the maximum input voltage.
The inductor value also has an effect on low current
operation. The transition to low current operation begins
when the inductor current reaches zero while the bottom
MOSFET is on. Burst Mode operation begins when the
average inductor current required results in a peak current
0
0
100 200 300 400 500
OPERATING FREQUENCY (kHZ)
600
below 25% of the current limit determined by R SENSE .
Lower inductor values (higher ? I L ) will cause this to occur
1735-1 F02
Figure 2. Timing Capacitor Value
When synchronized to an external clock, Burst Mode
at higher load currents, which can cause a dip in efficiency
in the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
operation is disabled but the inductor current is not
allowed to reverse. The 25% minimum inductor current
11
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