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| 型号： | LTC1743IFW#TR |
| 厂商： | Linear Technology |
| 文件页数： | 6/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 50MSPS SMPL 48TSSOP |
| 标准包装： | 1,800 |
| 位数： | 12 |
| 采样率（每秒）： | 50M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 1.2W |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 48-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，双极；1 个差分，双极 |
14
LTC1743
1743f
APPLICATIO S I FOR ATIO
WU
U
Common Mode Bias
The ADC sample-and-hold circuit requires differential drive
to achieve specified performance. Each input should swing
±0.8Vforthe3.2Vrangeor±0.5Vforthe2Vrange,around
a common mode voltage of 2.5V. The VCM output pin
(Pin 2) may be used to provide the common mode bias
level. VCM can be tied directly to the center tap of a trans-
former to set the DC input level or as a reference level to
an op amp differential driver circuit. The VCM pin must be
bypassed to ground close to the ADC with 4.7
Forgreater.
Input Drive Impedance
As with all high performance, high speed ADCs the dy-
namic performance of the LTC1743 can be influenced by
the input drive circuitry, particularly the second and third
harmonics. Source impedance and input reactance can
influence SFDR. At the falling edge of encode the sample-
and-hold circuit will connect the 7pF sampling capacitor to
the input pin and start the sampling period. The sampling
period ends when encode rises, holding the sampled input
on the sampling capacitor. Ideally the input circuitry
should be fast enough to fully charge the sampling capaci-
tor during the sampling period 1 / (2Fencode); however,
this is not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recomended to have a
source impedence of 100
or less for each input. The
source impedence should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC1743 being driven by an RF
transformer with a center tapped secondary. The second-
ary center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used if the
source impedence seen by the ADC does not exceed
100
for each ADC input. A disadvantage of using a
transformer is the loss of low frequency response. Most
small RF transformers have poor performance at frequen-
cies below 1MHz.
1:1
37
0.1
F
ANALOG
INPUT
VCM
AIN
+
AIN
–
100
100
18pF
1743 F03
4.7
F
37
LTC1743
Figure 3. Single-Ended to Differential
Conversion Using a Transformer
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| LTC1744CFW#PBF | 功能描述:IC ADC 14BIT 50MSPS 48-TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
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| LTC1744CFW#TRPBF | 功能描述:IC ADC 14BIT 50MSPS 48-TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
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