参数资料
型号: LTC1749CFW#TRPBF
厂商: Linear Technology
文件页数: 1/20页
文件大小: 0K
描述: IC ADC 12BIT 80MSPS SMPL 48TSSOP
标准包装: 1,800
位数: 12
采样率(每秒): 80M
数据接口: 并联
转换器数目: 1
功率耗散(最大): 1.69W
电压电源: 单电源
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-TFSOP(0.240",6.10mm 宽)
供应商设备封装: 48-TSSOP
包装: 带卷 (TR)
输入数目和类型: 2 个单端,双极;1 个差分,双极
1
LTC1749
1749f
12-Bit, 80Msps
Wide Bandwidth ADC
s
Sample Rate: 80Msps
s
PGA Front End (2.25VP-P or 1.35VP-P Input Range)
s
71.8dB SNR and 87dB SFDR (PGA = 0)
s
70.2dB SNR and 87dB SFDR (PGA = 1)
s
500MHz Full Power Bandwidth S/H
s
No Missing Codes
s
Single 5V Supply
s
Power Dissipation: 1.45W
s
Two Pin Selectable Reference Values
s
Data Ready Output Clock
s
Pin Compatible 14-Bit 80Msps Device (LTC1750)
s
48-Pin TSSOP Package
s
Direct IF Sampling
s
Telecommunications
s
Receivers
s
Cellular Base Stations
s
Spectrum Analysis
s
Communications Test Equipment
s
Undersampling
, LTC and LT are registered trademarks of Linear Technology Corporation.
The LTC
1749 is an 80Msps, 12-bit A/D converter de-
signed for digitizing wide dynamic range signals up to
frequencies of 500MHz. The input range of the ADC can be
optimized with the on-chip PGA sample-and-hold circuit
and flexible reference circuitry.
The LTC1749 has a highly linear sample-and-hold circuit
with a bandwidth of 500MHz. The SFDR is 80dB with an
input frequency of 250MHz. Ultralow jitter of 0.15psRMS
allows undersampling of IF frequencies with minimal
degradation in SNR. DC specs include
±1LSB INL and no
missing codes.
The digital interface is compatible with 5V, 3V, 2V and
LVDS logic systems. The ENC and ENC inputs may be
driven differentially from PECL, GTL and other low swing
logic families or from single-ended TTL or CMOS. The low
noise, high gain ENC and ENC inputs may also be driven
by a sinusoidal signal without degrading performance. A
separate output power supply can be operated from 0.5V
to 5V, making it easy to connect directly to low voltage
DSPs or FIFOs.
The 48-pin TSSOP package with a flow-through pinout
simplifies the board layout.
80Msps, 12-Bit ADC with a 2.25V Differential Input Range
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
BLOCK DIAGRA
W
12-BIT
PIPELINED ADC
12
S/H
CIRCUIT
±1.125V
DIFFERENTIAL
ANALOG INPUT
AIN
+
PGA
AIN
SENSE
VCM
4.7
F
DIFF AMP
REFLA
REFHB
GND
1749 BD
ENC
4.7
F
1
F1F
0.1
F
0.1
F
REFHA
REFLB
BUFFER
RANGE
SELECT
2VREF
CORRECTION
LOGIC AND
SHIFT
REGISTER
OUTPUT
LATCHES
CONTROL LOGIC
OVDD
VDD
OGND
0.5V TO 5V
5V
0.1
F
1
F
1
F
1
F
D11
D0
CLKOUT
ENC
DIFFERENTIAL
ENCODE INPUT
MSBINV
0.1
F
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