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| 型号： | LTC1751EMS8#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/12页 |
| 文件大小： | 0K |
| 描述： | IC REG SWITCHD CAP DBL ADJ 8MSOP |
| 标准包装： | 50 |
| 类型： | 切换式电容器（充电泵），倍增器 |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调 |
| 输入电压： | 2.5 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 800kHz |
| 电流 - 输出： | 125mA |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 包装： | 管件 |
| 供应商设备封装： | 8-MSOP |
| 产品目录页面： | 1339 (CN2011-ZH PDF) |
LTC1751/LTC1751-3.3/LTC1751-5
APPLICATIO S I FOR ATIO
There are several ways to reduce output voltage ripple.
For applications requiring V IN to exceed 3.3V or for
applications requiring < 100mV of peak-to-peak ripple, a
larger C OUT capacitor (22 μ F or greater) is recommended.
A larger capacitor will reduce both the low and high
frequency ripple due to the lower charging and discharg-
ing slew rates as well as the lower ESR typically found
with higher value (larger case size) capacitors. A low ESR
ceramic output capacitor will minimize the high fre-
quency ripple, but will not reduce the low frequency
ripple unless a high capacitance value is used. An R-C
filter may also be used to reduce high frequency voltages
spikes (see Figure 1).
various parameters such as temperature, output loading,
charge pump and flying capacitor values and input
voltage.
PGOOD and Undervoltage Detection
The PGOOD pin on the LTC1751-3.3/LTC1751-5 performs
two functions. On start-up, it indicates when the output
has reached its final regulation level. After start-up, it
indicates when a fault condition, such as excessive load-
ing, has pulled the output out of regulation.
Once the LTC1751-3.3/LTC1751-5 are enabled via the
SHDN pin, V OUT ramps to its final regulation value slowly
by following the SS pin. The PGOOD pin switches from low
V OUT
LTC1751-X
+
1 ?
10 μ F
TANT
+
10 μ F
TANT
V OUT
5V
impedance to high impedance after V OUT reaches its
regulation value. If V OUT is subsequently pulled below its
correct regulation level, the PGOOD pin pulls low again
1751 F01
Figure 1. Output Ripple Reduction Technique
Note that when using a larger output capacitor the mini-
mum turn-on time of the device will increase.
Soft-Start
The LTC1751 family has built-in soft-start circuitry to
prevent excessive current flow at V IN during start-up. The
soft-start time is programmed by the value of the capacitor
at the SS pin. Typically a 2 μ A current is forced out of SS
causing a ramp voltage on the SS pin. The regulation loop
follows this ramp voltage until the output reaches the
correct regulation level. SS is automatically pulled to
ground whenever SHDN is low. The typical rise time is
given by the expression:
t r = 0.6ms/nF ? C SS
indicating that a fault exists. Alternatively, if there is a short
circuit on V OUT preventing it from ever reaching its correct
regulation level, the PGOOD pin will remain low. The lower
fault threshold, UVL, is preprogrammed to recognize
errors of – 7% below nominal V OUT . The upper fault
threshold, UVH, is preprogrammed at – 4.5% below nomi-
nal. Figure 2 shows an example of the PGOOD pin with a
normal start-up followed by an undervoltage fault.
Using an external pull-up resistor, the PGOOD pin can be
pulled high from any available voltage supply, including
the LTC1751-3.3/LTC1751-5 V OUT pin.
If PGOOD is not used it may be connected to GND.
SHDN
PGOOD
t r
For example, with a 4.7nF capacitor the 10% to 90% rise
V OUT
90%
UVL
time will be approximately 2.8ms. If the output charge
storage capacitor is 10 μ F, then the average output current
for an LTC1751-5 will be 4V/2.8ms ? 10 μ F or 14mA, giving
28mA at the V IN pin.
10%
UVH
The soft-start feature is optional. If there is no capacitor
on SS, the output voltage of the LTC1751 will ramp up as
TIME
17515 F02
quickly as possible. The start-up time will depend on
Figure 2. PGOOD During Start-Up and Undervoltage
9
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