参数资料
型号: LTC1771ES8#PBF
厂商: Linear Technology
文件页数: 12/16页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 8-SOIC
标准包装: 100
PWM 型: 电流模式
输出数: 1
占空比: 100%
电源电压: 2.8 V ~ 18 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 管件
产品目录页面: 1333 (CN2011-ZH PDF)
LTC1771
APPLICATIO S I FOR ATIO
? I L = 3 . 5 μ s ?
? = 0 . 89 A
2. Is the 0.1μF input decoupling capacitor closely con-
nected between V IN (Pin 6) and ground (Pin 4)? This
capacitor carries the high frequency peak currents.
3. Does the V FB pin connect directly to the feedback
resistors? The resistive divider R1 and R2 must be
connected between the (+) plate of C OUT and signal
ground. Locate the feedback resistors right next to the
LTC1771. The V FB line should not be routed close to any
nodes with high slew rates.
4. Is the 1000pF decoupling capacitor for the current
sense resistor connected as close as possible to Pins 6
and 7? Ensure accurate current sensing with Kelvin
connections to the sense resistor.
5. Is the (+) plate of C IN closely connected to the sense
resistor ? This capacitor provides the AC current to the
MOSFET.
6. Are the signal and power grounds segregated? The
signal ground consists of the (–) plate of C OUT , Pin 4 of
the LTC1771 and the resistive divider. The power ground
consists of the Schottky diode anode and the (–) plate
of C IN which should have as short lead lengths as
possible.
7. Keep the switching node (SW) and the gate node
(PGATE) away from sensitive small signal nodes, espe-
cially the voltage sensing feedback pin (V FB ), and mini-
Design Example
As a design example, assume V IN = 10V (nominal), V IN =
15V (MAX) , V OUT = 3.3V, and I MAX = 2A. With this informa-
tion, we can easily calculate all the important components.
R SENSE = 100mV/2A = 0.05 ?
To optimize low current efficiency, MODE pin is tied to V IN
to enable Burst Mode operation, thus the minimum induc-
tance necessary is:
L MIN = 70 μ H(3.3V + 0.5)(0.05 ? ) = 13.3 μ H
15 μ H is chosen for the application.
? 3 . 3 V + 0 . 5 V ?
? 15 μ H ?
For the feedback resistors, choose R1 = 1M to minimize
supply current. R2 can then be calculated to be:
R2 = (V OUT /1.23 – 1) ? R1 = 1.68M
Assume that the MOSFET dissipation is to be limited to
P P = 0.25W.
If T A = 70 ° C and the thermal resistance of the MOSFET is
83 ° C/W, then the junction temperatures will be 91 ° C and
δ P = 0.33. The required R DS(ON) for the MOSFET can now
be calculated:
P - Channel R DS(ON) =
( )( )
? 3 . 3 V + 0 . 5 V ?
? 2 A
?
mize their PC trace area.
C SS
1
RUN/SS MODE
C ITH
R ITH 2
I TH SENSE
8
7
MODE
0 . 25 W
? 10 V + 0 . 5 V ?
= 0 . 130 ?
2
1 . 33
R1
3
4
V FB
GND
LTC1771
V IN
PGATE
6
5
+
C IN D1
Q1
Since the gate of the MOSFET will see the full input voltage,
a MOSFET must be selected whose V GS(MAX) > 15V. A
P-channel MOSFET that meets both the V GS(MAX) and
R2
C FF
0.1 μ F
C OUT
L
R DS(ON) requirement is the Si6447DQ.
The most stringent requirement for the Schottky diode
P D = I SC ( AVG ) ( V D ) ?
? V IN + V D ?
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 5. LTC1771 Layout Diagram
12
V OUT
1771 F05
occurs when V OUT = 0V (i.e., short circuit) at maximum
V IN . In this case the worst-case dissipation rises to:
? V IN ?
?
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