参数资料
型号: LTC1772ES6#TRPBF
厂商: Linear Technology
文件页数: 7/12页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM SOT23-6
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 650kHz
占空比: 100%
电源电压: 2.5 V ~ 9.8 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: SOT-23-6 细型,TSOT-23-6
包装: 带卷 (TR)
LTC1772
APPLICATIO N S I N FOR M ATIO N
I RIPPLE ≤
wherefistheoperatingfrequency.Acceptinglargervalues
of I RIPPLE allows the use of low inductances, but results in
higher output voltage ripple and greater core losses. A
reasonable starting point for setting ripple current is
I RIPPLE = 0.4(I OUT(MAX) ). Remember, the maximum I RIPPLE
occurs at the maximum input voltage.
In Burst Mode operation on the LTC1772, the ripple
current is normally set such that the inductor current is
continuous during the burst periods. Therefore, the peak-
to-peak ripple current must not exceed:
0 . 03
R SENSE
This implies a minimum inductance of:
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu-
facturer is Kool M μ . Toroids are very space efficient,
especially when you can use several layers of wire. Be-
cause they generally lack a bobbin, mounting is more
difficult. However, new designs for surface mount that do
not increase the height significantly are available.
Power MOSFET Selection
An external P-channel power MOSFET must be selected
for use with the LTC1772. The main selection criteria for
the power MOSFET are the threshold voltage V GS(TH) and
the “on” resistance R DS(ON) , reverse transfer capacitance
C RSS and total gate charge.
V IN ? V OUT ? V OUT + V D ?
? 0 . 03 ? ? V IN D ?
+ V
? R SENSE ?
L MIN =
f ? ?
? ?
Since the LTC1772 is designed for operation down to low
input voltages, a sublogic level threshold MOSFET (R DS(ON)
guaranteed at V GS = 2.5V) is required for applications that
work close to this voltage. When these MOSFETs are used,
(Use V IN(MAX) = V IN )
A smaller value than L MIN could be used in the circuit;
however, the inductor current will not be continuous
during burst periods.
Inductor Core Selection
make sure that the input supply to the LTC1772 is less than
the absolute maximum V GS rating, typically 8V.
The required minimum R DS(ON) of the MOSFET is gov-
erned by its allowable power dissipation. For applications
that may operate the LTC1772 in dropout, i.e., 100% duty
cycle, at its worst case the required R DS(ON) is given by:
R DS ( ON )
OncethevalueforLisknown,thetypeofinductormustbe
selected. High efficiency converters generally cannot af-
ford the core loss found in low cost powdered iron cores,
DC = 100 %
=
P P
( I OUT ( MAX ) ) 2 ( 1 + δ p )
forcing the use of more expensive ferrite, molypermalloy
or Kool M μ ? cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will in-
crease. Ferrite designs have very low core losses and are
preferred at high switching frequencies, so design goals
can concentrate on copper loss and preventing saturation.
where P P is the allowable power dissipation and δ p is the
temperature dependency of R DS(ON) . (1 + δ p) is generally
given for a MOSFET in the form of a normalized R DS(ON) vs
temperature curve, but δ p = 0.005/ ° C can be used as an
approximation for low voltage MOSFETs.
In applications where the maximum duty cycle is less than
100% and the LTC1772 is in continuous mode, the R DS(ON)
is governed by:
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in
R DS ( ON ) ?
P P
( DC ) I OUT 2 ( 1 + δ p )
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
where DC is the maximum operating duty cycle of the
LTC1772.
1772fb
7
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