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参数资料
| 型号： | LTC1863LIGN#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 16/16页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 8CH 175KSPS 16SSOP |
| 标准包装： | 100 |
| 位数： | 12 |
| 采样率（每秒）： | 175k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 2.7mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SSOP |
| 包装： | 管件 |
| 输入数目和类型： | 8 个单端，单极；8 个单端，双极；4 个差分，单极；4 个差分，双极 |
LTC1863L/LTC1867L
9
1863l7lfc
APPLICATIONS INFORMATION
Overview
The LTC1863L/LTC1867L are complete, low power, multi-
plexed ADCs. They consist of a 12-/16-bit, 175ksps capaci-
tive successive approximation A/D converter, a precision
internal reference, a congurable 8-channel analog input
multiplexer (MUX) and a serial port for data transfer.
Conversions are started by a rising edge on the CS/CONV
input. Once a conversion cycle has begun, it cannot be
restarted. Between conversions, the ADCs receive an input
word for channel selection and output the conversion
result, and the analog input is acquired in preparation for
the next conversion. In the acquire phase, a minimum time
of 2.01μs will provide enough time for the sample-and-hold
capacitors to acquire the analog signal.
During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from
the most signicant bit (MSB) to the least signicant bit
(LSB). The input is sucessively compared with the binary
weighted charges supplied by the differential capacitive
DAC. Bit decisions are made by a low power, differential
comparator that rejects common mode noise. At the end
of a conversion, the DAC output balances the analog input.
The SAR content (a 12-/16-bit data word) that represents
the analog input is loaded into the 12-/16-bit output latches.
Analog Input Multiplexer
The analog input multiplexer is controlled by a 7-bit input
data word. The input data word is dened as follows:
SD OS S1
S0 COM UNI SLP
SD = SINGLE/DIFFERENTIAL BIT
OS = ODD/SIGN BIT
S1 = ADDRESS SELECT BIT 1
S0 = ADDRESS SELECT BIT 0
COM = CH7/COM CONFIGURATION BIT
UNI = UNIPOLAR/BIPOLAR BIT
SLP = SLEEP MODE BIT
Examples of Multiplexer Options
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
GND (
–)
8 Single-Ended
+
4 Differential
+ (–)
+
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM (
–)
7 Single-Ended
to CH7/COM
+
+ (–)
– (+)
GND (
–)
Combinations of Differential
and Single-Ended
+
–
{
1863L7L
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
Tables 1 and 2 show the congurations when COM = 0,
and COM = 1.
Table 1. Channel Conguration (When COM = 0, CH7/COM Pin
Is Used as CH7)
SD
OS
S1
S0
COM
Channel Conguration
“+”
“–”
00
0
CH0
CH1
00
0
1
0
CH2
CH3
00
1
0
CH4
CH5
00
1
0
CH6
CH7
01
0
CH1
CH0
01
0
1
0
CH3
CH2
01
1
0
CH5
CH4
01
1
0
CH7
CH6
10
0
CH0
GND
10
0
1
0
CH2
GND
10
1
0
CH4
GND
10
1
0
CH6
GND
11
0
CH1
GND
11
0
1
0
CH3
GND
11
1
0
CH5
GND
11
1
0
CH7
GND
CH7/COM
(UNUSED)
CH7/COM (
–)
1st Conversion
2nd Conversion
+
–
+
–
+
–
+
{
CH2
CH3
CH4
CH5
CH2
CH3
CH4
CH5
1863L7L AI02
Changing the MUX Assignment “On the Fly”
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