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参数资料
| 型号： | LTC1922IG-1#TR |
| 厂商： | Linear Technology |
| 文件页数： | 12/24页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR ISO PWM 20-SSOP |
| 标准包装： | 1,800 |
| PWM 型： | 电流/电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 99% |
| 电源电压： | 3.8 V ~ 10.3 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-SSOP（0.209"，5.30mm 宽） |
| 包装： | 带卷 (TR) |
LTC1922-1
OPERATIO
PDLY corresponding to several volts across the MOSFET,
the LTC1922-1 can “anticipate” a zero voltage VDS and
signal the external driver and switch to turn-on. The
amount of anticipation can be tailored for any application
by modifying the upper divider resistor(s). The LTC1922-1
DirectSense circuitry sources a trimmed current out of
PDLY and ADLY after a low to high level transition occurs.
This provides hysteresis and noise immunity for the PDLY
and ADLY circuitry, and sets the high to low threshold on
ADLY or PDLY to nearly the same level as the low to high
threshold, thereby making the upper and lower MOSFET
VDS switch points virtually identical, independent of V IN .
Example: V IN = 48V nominal (36V to 72V)
1. Set up SBUS: 1.5V is desired on SBUS with V IN = 48V.
Set divider current to 100 μ A.
R1 = 1.5V/100 μ A = 15k.
to V CC as well as signaling that the chip’s bias voltage is
sufficient to begin switching operation (under voltage
lockout). With its typical 10.2V turn-on voltage and 4.2V
UVLO hysteresis, the LTC1922-1 is tolerant of loosely
regulated input sources such as an auxiliary transformer
winding. The V CC shunt is capable of sinking up to 25mA
of externally applied current. The UVLO turn-on and turn-
off thresholds are derived from an internally trimmed
reference making them extremely accurate. In addition,
the LTC1922-1 exhibits very low (145 μ A typ) start-up
current that allows the use of 1/8W to 1/4W trickle charge
start-up resistors.
The trickle charge resistor should be selected as follows:
R START(MAX) = V IN(MIN) – 10.7V/250 μ A
Adding a small safety margin and choosing standard
values yields:
R2 = (48V – 1.5V)/100 μ A = 465k.
An optional small capacitor (0.001 μ F) can be added
across R1 to decouple noise from this input.
2. Set up ADLY and PDLY: 7V of “anticipation” are required
APPLICATION
DC/DC
Off-Line
PFC Preregulator
V IN RANGE
36V to 72V
85V to 270V RMS
390V DC
R START
100k
430k
1.4M
in this circuit to account for the delays of the external
MOSFET driver and gate drive components.
R3, R4 = 1k, sets a nominal 1.5mA in the divider
chain at the threshold.
R5, R6 = (48V – 7V – 1.5V)/1.5mA = 26.3k,
use (2) equal 13k segments.
Zero Delay Mode
The LTC1922-1 provides the flexibility through the SBUS
pin to disable the DirectSense delay circuitry. See Figure 3
for details.
V REF
V CC should be bypassed with a 0.1 μ F to 1 μ F multilayer
ceramic capacitor to decouple the fast transient currents
demanded by the output drivers and a bulk tantalum or
electrolytic capacitor to hold up the V CC supply before the
bootstrap winding, or an auxiliary regulator circuit takes
over.
C HOLDUP = (I CC + I DRIVE ) ? t DELAY /3.8V
(minimum UVLO hysteresis)
Regulated bias supplies as low as 7V can be utilized to
provide bias to the LTC1922-1. Refer to Figure 4 for
various bias supply configurations.
SBUS
ADLY
12V ± 10%
V BIAS < V UVLO
V IN
PDLY
1922 F03
1.5k
1N5226
3V
1N914
R START
Figure 3. Zero Delays
0.1 μ F
0.1 μ F
+
C HOLD
Powering the LTC1922-1
The LTC1922-1 utilizes an integrated V CC shunt regulator
to serve the dual purposes of limiting the voltage applied
V CC
V CC
Figure 4. Bias Configurations
1922 F04
12
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