参数资料
型号: LTC2170IUKG-12#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: ADC
英文描述: 4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC52
封装: 7 X 8 MM, LEAD FREE, PLASTIC, QFN-52
文件页数: 1/34页
文件大小: 1304K
代理商: LTC2170IUKG-12#PBF
LTC2172-12/
LTC2171-12/LTC2170-12
1
21721012fb
Typical applicaTion
DescripTion
12-Bit, 65Msps/40Msps/
25Msps Low Power Quad ADCs
TheLTC2172-12/LTC2171-12/LTC2170-12are4-channel,
simultaneoussampling12-bitA/Dconvertersdesignedfor
digitizinghighfrequency,widedynamicrangesignals.They
are perfect for demanding communications applications
with AC performance that includes 71dB SNR and 90dB
spurious free dynamic range (SFDR). An ultralow jitter of
0.15psRMS allows undersampling of IF frequencies with
excellent noise performance.
DC specifications include ±0.3LSB INL (typ), ±0.1LSB
DNL (typ) and no missing codes over temperature. The
transition noise is a low 0.3LSBRMS.
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode) or one bit at a time (1-lane mode). The LVDS
drivers have optional internal termination and adjustable
output levels to ensure clean signal integrity.
The ENC+ and ENCinputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
LTC2172-12, 65Msps,
2-Tone FFT, fIN = 70MHz and 75MHz
FeaTures
applicaTions
n
4-Channel Simultaneous Sampling ADC
n
71dB SNR
n
90dB SFDR
n
Low Power: 306mW/198mW/160mW Total,
77mW/50mW/40mW per Channel
n
Single 1.8V Supply
n
Serial LVDS Outputs: One or Two Bits per Channel
n
Selectable Input Ranges: 1VP-P to 2VP-P
n
800MHz Full Power Bandwidth Sample-and-Hold
n
Shutdown and Nap Modes
n
Serial SPI Port for Configuration
n
Pin-Compatible 14-Bit and 12-Bit Versions
n
52-Pin (7mm × 8mm) QFN Package
n
Communications
n
Cellular Base Stations
n
Software Defined Radios
n
Portable Medical Imaging
n
Multichannel Data Acquisition
n
Nondestructive Testing
DATA
SERIALIZER
ENCODE
INPUT
SERIALIZED
LVDS
OUTPUTS
1.8V
VDD
1.8V
OVDD
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
OUT3B
OUT4A
OUT4B
DATA
CLOCK
OUT
FRAME
OGND
GND
217212 TA01
S/H
CHANNEL 1
ANALOG
INPUT
12-BIT
ADC CORE
S/H
CHANNEL 2
ANALOG
INPUT
12-BIT
ADC CORE
S/H
CHANNEL 3
ANALOG
INPUT
12-BIT
ADC CORE
S/H
CHANNEL 4
ANALOG
INPUT
12-BIT
ADC CORE
PLL
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE
(dBFS) –50
–30
–40
–20
–10
0
10
20
30
217212 TA01b
L
, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
相关PDF资料
PDF描述
LTC2171CUKG-12#TRPBF 4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC52
LTC2171IUKG-12#TRPBF 4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC52
LTC2172CUKG-12#PBF 4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC52
LTC2170CUKG-12#PBF 4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC52
LTC2170IUKG-12#TRPBF 4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC52
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