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参数资料
| 型号： | LTC2175IUKG-14#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 15/34页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 125MSPS QUAD 52QFN |
| 标准包装： | 2,000 |
| 位数： | 14 |
| 采样率（每秒）： | 125M |
| 数据接口： | Serial LVDS |
| 转换器数目： | 4 |
| 功率耗散（最大）： | 646mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 52-WFQFN 裸露焊盘 |
| 供应商设备封装： | 52-QFN（7x8） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 Differential; 2 Single-Ended |
| 配用： | DC1371A-ND - BOARD USB DATA ACQUISITION HS |
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LTC2175-14/
LTC2174-14/LTC2173-14
22
21754314fa
applicaTions inForMaTion
The differential encode mode is recommended for sinu-
soidal, PECL, or LVDS encode inputs (Figures 12 and 13).
The encode inputs are internally biased to 1.2V through
10k equivalent resistance. The encode inputs can be taken
above VDD (up to 3.6V), and the common mode range is
from 1.1V to 1.6V. In the differential encode mode, ENC–
should stay at least 200mV above ground to avoid falsely
triggering the single-ended encode mode. For good jitter
performance ENC+ should have fast rise and fall times.
Thesingle-endedencodemodeshouldbeusedwithCMOS
encode inputs. To select this mode, ENC– is connected
to ground and ENC+ is driven with a square wave encode
input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V
to3.3VCMOSlogiclevelscanbeused.TheENC+threshold
is 0.9V. For good jitter performance ENC+ should have fast
rise and fall times.
Clock PLL and Duty Cycle Stabilizer
The encode clock is multiplied by an internal phase-locked
loop (PLL) to generate the serial digital output data. If the
encode signal changes frequency or is turned off, the PLL
requires 25s to lock onto the input clock.
A clock duty cycle stabilizer circuit allows the duty cycle
of the applied encode signal to vary from 30% to 70%.
In the serial programming mode it is possible to disable
the duty cycle stabilizer, but this is not recommended. In
the parallel programming mode the duty cycle stabilizer
is always enabled.
Figure 13. PECL or LVDS Encode Drive
Figure 12. Sinusoidal Encode Drive
50
100
0.1F
T1
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
50
LTC2175-14
217514 F12
ENC–
ENC+
ENC+
ENC–
PECL OR
LVDS
CLOCK
0.1F
217514 F13
LTC2175-14
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2180 | 制造商:LINER 制造商全称:Linear Technology 功能描述:12-Bit, 65Msps/ 40Msps/25Msps Low Power Dual ADCs |
| LTC2180CUP#PBF | 制造商:Linear Technology 功能描述:ADC Dual 25Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT DUAL PAR/SRL 64QFN 制造商:Linear Technology 功能描述:ADC 2CH 16BIT 25MSPS QFN-6 制造商:Linear Technology 功能描述:ADC, 2CH, 16BIT, 25MSPS, QFN-64 制造商:Linear Technology 功能描述:ADC, 2CH, 16BIT, 25MSPS, QFN-64; Resolution (Bits):16bit; Sampling Rate:25MSPS; Supply Voltage Type:Single; Supply Voltage Min:1.7V; Supply Voltage Max:1.9V; Supply Current:43.5mA; Digital IC Case Style:QFN; No. of Pins:64 ;RoHS Compliant: Yes |
| LTC2180CUP#PBF-ES | 制造商:Linear Technology 功能描述:ADC Dual 25Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP |
| LTC2180CUP#TRPBF | 制造商:Linear Technology 功能描述:ADC Dual 25Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC DUAL 16BIT 25MSPS 64-QFN |
| LTC2180CUP#TRPBF-ES | 制造商:Linear Technology 功能描述:ADC Dual 25Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R |
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