- 您现在的位置：买卖IC网 > PDF目录39413 > LTC2184CUP#PBF (LINEAR TECHNOLOGY CORP) 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 PDF资料下载
参数资料
| 型号： | LTC2184CUP#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封装： | 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64 |
| 文件页数： | 1/36页 |
| 文件大小： | 799K |
| 代理商： | LTC2184CUP#PBF |
当前第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
1
218543f
LTC2185/LTC2184/LTC2183
Typical applicaTion
FeaTures
applicaTions
DescripTion
16-Bit, 125/105/80Msps
Low Power Dual ADCs
n
Communications
n
Cellular Base Stations
n
Software Defined Radios
n
Portable Medical Imaging
n
Multi-Channel Data Acquisition
n
Nondestructive Testing
n
Two-Channel Simultaneously Sampling ADC
n
76.8dB SNR
n
90dB SFDR
n
Low Power: 370mW/308mW/200mW Total
185mW/154mW/100mW per Channel
n
Single 1.8V Supply
n
CMOS, DDR CMOS, or DDR LVDS Outputs
n
Selectable Input Ranges: 1VP-P to 2VP-P
n
550MHz Full Power Bandwidth S/H
n
Optional Data Output Randomizer
n
Optional Clock Duty Cycle Stabilizer
n
Shutdown and Nap Modes
n
Serial SPI Port for Configuration
n
64-Pin (9mm
× 9mm) QFN Package
The LTC2185/LTC2184/LTC2183 are two-channel si-
multaneous sampling 16-bit A/D converters designed for
digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 76.8dB SNR and
90dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.07psRMSallowsundersamplingofIFfrequencieswith
excellent noise performance.
DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 3.4LSBRMS.
The digital outputs can be either full rate CMOS, Double
Data Rate CMOS, or Double Data Rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L
, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
2-Tone FFT, fIN = 70MHz and 69MHz
CMOS,
DDR CMOS
OR DDR LVDS
OUTPUTS
1.8V
VDD
1.8V
OVDD
CLOCK
CONTROL
D1_15
D1_0
218543 TA01a
CH 1
ANALOG
INPUT
OUTPUT
DRIVERS
GND
OGND
S/H
16-BIT
ADC CORE
CH 2
ANALOG
INPUT
S/H
16-BIT
ADC CORE
D2_15
D2_0
125MHz
CLOCK
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE
(dBFS) –50
–30
–40
–20
–10
0
10
20
30
40
50
60
218543 TA01b
相关PDF资料 |
PDF描述 |
|---|---|
| LTC2184IUP#TRPBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2183CUP#TRPBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2184IUP#PBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2185IUP#PBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2183IUP#PBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2184IUP#PBF | 制造商:Linear Technology 功能描述:ADC Dual 105Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT 105M PAR/SRL 64-QFN |
| LTC2184IUP#PBF-ES | 制造商:Linear Technology 功能描述:ADC Dual 105Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP |
| LTC2184IUP#TRPBF | 制造商:Linear Technology 功能描述:ADC Dual 105Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16BIT 105M PAR/SRL 64-QFN |
| LTC2184IUP#TRPBF-ES | 制造商:Linear Technology 功能描述:ADC Dual 105Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R |
| LTC2184IUPPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 125/105/80Msps Low Power Dual ADCs |
发布紧急采购，3分钟左右您将得到回复。