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参数资料
| 型号： | LTC2204I |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
| 封装： | 7 X7 MM, PLASTIC, MO-220, QFN-48 |
| 文件页数： | 17/28页 |
| 文件大小： | 804K |
| 代理商： | LTC2204I |
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LTC2205/LTC2204
24
22054p
The lower limit of the LTC2205/LTC2204 sample rate is
determined by droop of the sample and hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specied minimum operating
frequency for the LTC2205/LTC2204 is 1Msps.
DIGITAL OUTPUTS
Digital Output Buffers
Figure 11 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated
from the ADC power and ground. The additional N-channel
transistor in the output driver allows operation down to
low voltages. The internal resistor in series with the output
eliminates the need for external damping resistors.
As with all high speed/high resolution converters, the digi-
tal output loading can affect the performance. The digital
outputs of the LTC2205/LTC2204 should drive a minimum
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as a ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF. A resistor in series with the
output may be used but is not required since the ADC has
a series resistor of 33Ω on chip.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
22054 F10
ENC–
ENC+
3.3V
D0
Q0
MC100LVELT22
LTC2205/
LTC2204
Figure 10. ENC Drive Using a CMOS to PECL Translator
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2205 is 65Msps.
The maximum encode rate for the LTC2204 is 40Msps.
For the ADC to operate properly the encode signal should
have a 50% (±2.5%) duty cycle. Achieving a precise 50%
duty cycle is easy with differential sinusoidal drive using
a transformer or using symmetric differential logic such
as PECL or LVDS. When using a single-ended ENCODE
signal asymmetric rise and fall times can result in duty
cycles that are far from 50%.
An optional clock duty cycle stabilizer can be used if the
input clock does not have a 50% duty cycle. This circuit
uses the rising edge of ENC pin to sample the analog input.
The falling edge of ENC is ignored and an internal falling
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 30% to 70% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin must be
connected to 1/3VDD or 2/3VDD using external resistors.
Figure 9. Single-Ended ENC Drive,
Not Recommended for Low Jitter
22054 F09
ENC–
1.6V
VTHRESHOLD = 1.6V
ENC+
0.1
F
LTC2205/
LTC2204
APPLICATIO S I FOR ATIO
WU
U
LTC2205/LTC2204
22054 F11
OVDD
VDD
0.1
F
TYPICAL
DATA
OUTPUT
OGND
OVDD
0.5V
TO VDD
PREDRIVER
LOGIC
DATA
FROM
LATCH
33
Figure 11. Equivalent Circuit for a Digital Output Buffer
相关PDF资料 |
PDF描述 |
|---|---|
| LTC2205C#PBF | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
| LTC2205I#PBF | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
| LTC2205I#TRPBF | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
| LTC2205I#TR | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
| LTC2205I | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2204IUK | 制造商:Linear Technology 功能描述:ADC Single Pipelined 40Msps 16-bit Parallel 48-Pin QFN EP 制造商:Linear Technology 功能描述:MS-ADC/High Speed, 16-bit, 40Msps ADC |
| LTC2204IUK#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 40Msps 16-bit Parallel 48-Pin QFN EP 制造商:Linear Technology 功能描述:Single ADC Pipelined 40Msps 16-bit Parallel 48-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16-BIT 40MSPS 48-QFN 制造商:Linear Technology 功能描述:ADC 16BIT 40MSPS 48QFN 制造商:Linear Technology 功能描述:ADC, 16BIT, 40MSPS, 48QFN 制造商:Linear Technology 功能描述:MS-ADC/High Speed, 16-bit, 40Msps ADC 制造商:Linear Technology 功能描述:IC, ADC, 16BIT, 40MSPS, QFN-48, Resolution (Bits):16bit, Sampling Rate:45MSPS, Supply Voltage Type:Single, Supply Voltage Min:3.135V, Supply Voltage Max:3.465V, Supply Current:145mA, Digital IC Case Style:QFN, No. of Pins:48 , RoHS Compliant: Yes |
| LTC2204IUK#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 40Msps 16-bit Parallel 48-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16-BIT 40MSPS 48-QFN |
| LTC2204IUK-PBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 65Msps/40Msps |
| LTC2204IUK-TR | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 65Msps/40Msps |
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