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参数资料
| 型号： | LTC2220IUP-1#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 10/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 185MSPS 64-QFN |
| 标准包装： | 2,000 |
| 位数： | 12 |
| 采样率（每秒）： | 185M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 1.18W |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-WFQFN 裸露焊盘 |
| 供应商设备封装： | 64-QFN（9x9） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个单端，双极; 1 个差分，双极 |
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18
LTC2220-1
2220_1fa
Other voltage ranges in between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 10. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
level as close to the converter as possible. If the SENSE pin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1
F ceramic capacitor.
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the amplitude.
3. If the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encode inputs so that any coupled noise will appear at both
inputs as common mode noise. The encode inputs have a
common mode range of 1.1V to 2.5V. Each input may be
driven from ground to VDD for single-ended drive.
APPLICATIO S I FOR ATIO
WU
UU
VDD
LTC2220-1
22201 F11
VDD
ENC–
ENC+
1.6V BIAS
1:4
0.1
F
CLOCK
INPUT
50
6k
TO INTERNAL
ADC CIRCUITS
Figure 11. Transformer Driven ENC+/ENC–
VCM
SENSE
1.6V
0.8V
2.2
F
12k
1
F
12k
22201 F10
LTC2220-1
Figure 10. 1.6V Range ADC
Input Range
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise perfor-
mance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 5dB. See the Typical Performance Character-
istics section.
Driving the Encode Inputs
The noise performance of the LTC2220-1 can depend on
the encode signal quality as much as on the analog input.
The ENC+/ENC– inputs are intended to be driven differen-
tially, primarily for noise immunity from common mode
noise sources. Each input is biased through a 6k resistor
to a 1.6V bias. The bias resistors set the DC operating point
for transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies) take the following into consideration:
1. Differential drive should be used.
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2220-1 is 185Msps.
For the ADC to operate properly, the encode signal should
have a 50% (
±5%) duty cycle. Each half cycle must have
at least 2.5ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise
50% duty cycle is easy with differential sinusoidal drive
using a transformer or using symmetric differential logic
such as PECL or LVDS.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the ENC+ pin to sample the analog
input. The falling edge of ENC+ is ignored and the internal
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary from 30% to 70% and the clock
duty cycle stabilizer will maintain a constant 50% internal
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