参数资料
型号: LTC2222CUK-11#PBF
厂商: Linear Technology
文件页数: 11/24页
文件大小: 0K
描述: IC ADC 11BIT 105MSPS SAMPL 48QFN
标准包装: 52
位数: 11
采样率(每秒): 105M
数据接口: 并联
转换器数目: 1
功率耗散(最大): 535mW
电压电源: 单电源
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-QFN-EP(7x7)
包装: 管件
输入数目和类型: 1 个单端,双极; 1 个差分,双极
LTC2222-11
19
222211f
APPLICATIO S I FOR ATIO
WU
UU
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply then OVDD should be tied to that same 1.8V supply.
OVDD can be powered with any voltage up to 3.6V. OGND
can be powered with any voltage from GND up to 1V and
must be less than OVDD. The logic outputs will swing be-
tween OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF and
CLOCKOUT. The data access and bus relinquish times are
too slow to allow the outputs to be enabled and disabled
during full speed operation. The output Hi-Z state is intended
for use during long periods of inactivity.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to VDD and OE to VDD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to VDD and OE
to GND results in nap mode, which typically dissipates
35mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
and nap mode all digital outputs are disabled and enter the
Hi-Z state.
GROUNDING AND BYPASSING
The LTC2222-11 requires a printed circuit board with a clean
unbroken ground plane. A multilayer board with an inter-
nal ground plane is recommended. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital signal alongside an
analog signal or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD,OVDD,VCM,REFHA,REFHB,REFLAandREFLBpins
as shown on the schematic on Page 20 of this data sheet.
Bypass capacitors must be located as close to the pins as
possible. Of particular importance are the capacitors be-
tween REFHA and REFLB and between REFHB and REFLA.
These capacitors should be as close to the device as pos-
sible (1.5mm or less). Size 0402 ceramic capacitors are
recommended. The 2.2
F capacitor between REFHA and
REFLA can be somewhat further away. The traces connect-
ing the pins and bypass capacitors must be kept short and
should be made as wide as possible.
The LTC2222-11 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
HEAT TRANSFER
Most of the heat generated by the LTC2222-11 is transferred
from the die through the bottom-side exposed pad and
package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad should
be soldered to a large grounded pad on the PC board. It is
critical that all ground pins are connected to a ground plane
of sufficient area.
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LTC2222IUK-11 制造商:LINER 制造商全称:Linear Technology 功能描述:11-Bit, 105Msps ADC