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参数资料
| 型号： | LTC2225CUH#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 5/20页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12-BIT 10MSPS 3V 32-QFN |
| 标准包装： | 73 |
| 位数： | 12 |
| 采样率（每秒）： | 10M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 69mW |
| 电压电源： | 单电源 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 管件 |
| 输入数目和类型： | 1 个单端，双极; 1 个差分，双极 |
| 产品目录页面： | 1349 (CN2011-ZH PDF) |
LTC2225
13
2225fa
APPLICATIO S I FOR ATIO
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An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary and the clock duty cycle stabilizer
will maintain a constant 50% internal duty cycle. If the
clock is turned off for a long period of time, the duty cycle
stabilizer circuit will require a hundred clock cycles for the
PLL to lock onto the input clock. To use the clock duty
cycle stabilizer, the MODE pin should be connected to
1/3VDD or 2/3VDD using external resistors.
The lower limit of the LTC2225 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating fre-
quency for the LTC2225 is 1Msps.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
level as close to the converter as possible. If the SENSE pin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1
F ceramic capacitor.
Input Range
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise perfor-
mance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 3.8dB.
Driving the Clock Input
The CLK input can be driven directly with a CMOS or TTL
level signal. A differential clock can also be used along with
a low-jitter CMOS converter before the CLK pin (see
Figure 8).
The noise performance of the LTC2225 can depend on the
clock signal quality as much as on the analog input. Any
noise present on the clock signal will result in additional
aperture jitter that will be RMS summed with the inherent
ADC aperture jitter.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2225 is 10Msps.
For the ADC to operate properly, the CLK signal should
have a 50% (
±10%) duty cycle. Each half cycle must have
at least 40ns for the ADC internal circuitry to have enough
settling time for proper operation.
Figure 8. CLK Drive Using an LVDS or PECL to CMOS Converter
CLK
100
0.1
F
4.7
F
FERRITE
BEAD
CLEAN
SUPPLY
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
2225 F08
LTC2225
Table 1. Output Codes vs Input Voltage
AIN
+ – AIN–
D11 – D0
(2V Range)
OF
(Offset Binary)
(2’s Complement)
>+1.000000V
1
1111 1111 1111
0111 1111 1111
+0.999512V
0
1111 1111 1111
0111 1111 1111
+0.999024V
0
1111 1111 1110
0111 1111 1110
+0.000488V
0
1000 0000 0001
0000 0000 0001
0.000000V
0
1000 0000 0000
0000 0000 0000
–0.000488V
0
0111 1111 1111
1111 1111 1111
–0.000976V
0
0111 1111 1110
1111 1111 1110
–0.999512V
0
0000 0000 0001
1000 0000 0001
–1.000000V
0
0000 0000 0000
1000 0000 0000
<–1.000000V
1
0000 0000 0000
1000 0000 0000
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| LTC2225IUH | 制造商:Linear Technology 功能描述:ADC Single Pipelined 10Msps 12-bit Parallel 32-Pin QFN EP |
| LTC2225IUH#PBF | 功能描述:IC ADC 12-BIT 10MSPS 3V 32-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:microPOWER™ 位数:8 采样率（每秒）:1M 数据接口:串行，SPI? 转换器数目:1 功率耗散（最大）:- 电压电源:模拟和数字 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:24-VFQFN 裸露焊盘 供应商设备封装:24-VQFN 裸露焊盘（4x4） 包装:Digi-Reel® 输入数目和类型:8 个单端，单极 产品目录页面:892 (CN2011-ZH PDF) 其它名称:296-25851-6 |
| LTC2225IUH#TR | 制造商:Linear Technology 功能描述:ADC Single Pipelined 10Msps 12-bit Parallel 32-Pin QFN EP T/R |
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