参数资料
型号: LTC2236CUH#PBF
厂商: Linear Technology
文件页数: 14/28页
文件大小: 0K
描述: IC ADC 10-BIT 25MSPS 3V 32-QFN
标准包装: 73
位数: 10
采样率(每秒): 25M
数据接口: 并联
转换器数目: 1
功率耗散(最大): 90mW
电压电源: 单电源
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 管件
输入数目和类型: 1 个单端,双极; 1 个差分,双极
产品目录页面: 1349 (CN2011-ZH PDF)
LTC2238/LTC2237/LTC2236
21
223876fa
Data Format
Using the MODE pin, the LTC2238/LTC2237/LTC2236
parallel digital output can be selected for offset binary or
2’s complement format. Connecting MODE to GND or
1/3VDD selects offset binary output format. Connecting
MODE to 2/3VDD or VDD selects 2’s complement output
format. An external resistor divider can be used to set the
1/3VDD or 2/3VDD logic values. Table 2 shows the logic
states for the MODE pin.
APPLICATIO S I FOR ATIO
WU
U
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to VDD and OE to VDD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to VDD and OE
to GND results in nap mode, which typically dissipates
15mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Grounding and Bypassing
The LTC2238/LTC2237/LTC2236 requires a printed cir-
cuit board with a clean, unbroken ground plane. A multi-
layer board with an internal ground plane is recom-
mended. Layout for the printed circuit board should en-
sure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capaci-
tors must be located as close to the pins as possible. Of
particular importance is the 0.1
F capacitor between
REFH and REFL. This capacitor should be placed as close
to the device as possible (1.5mm or less). A size 0402
ceramic capacitor is recommended. The large 2.2
F ca-
pacitor between REFH and REFL can be somewhat further
away. The traces connecting the pins and bypass capaci-
tors must be kept short and should be made as wide as
possible.
The LTC2238/LTC2237/LTC2236 differential inputs should
run parallel and close to each other. The input traces
should be as short as possible to minimize capacitance
and to minimize noise pickup.
Table 2. MODE Pin Function
Clock Duty
MODE Pin
Output Format
Cycle Stablizer
0
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply, then OVDD should be tied to that same 1.8V supply.
OVDD can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND up
to 1V and must be less than OVDD. The logic outputs will
swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF. The data ac-
cess and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed op-
eration. The output Hi-Z state is intended for use during long
periods of inactivity.
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