参数资料
型号: LTC2250CUH#TRPBF
厂商: Linear Technology
文件页数: 8/24页
文件大小: 0K
描述: IC ADC 10BIT 105MSPS 3V 32-QFN
标准包装: 2,500
位数: 10
采样率(每秒): 105M
数据接口: 并联
转换器数目: 1
功率耗散(最大): 378mW
电压电源: 单电源
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 带卷 (TR)
输入数目和类型: 1 个单端,双极; 1 个差分,双极
LTC2251/LTC2250
16
22510fa
APPLICATIO S I FOR ATIO
WU
UU
The difference amplifier generates the high and low refer-
ence for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins. The multiple output
pins are needed to reduce package inductance. Bypass
capacitors must be connected as shown in Figure 9.
Other voltage ranges in-between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 10. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
level as close to the converter as possible. If the SENSE pin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1
Fceramiccapacitor.
VCM
SENSE
1.5V
0.75V
2.2
F
12k
1
F
12k
22510 F10
LTC2251/
LTC2250
Figure 10. 1.5V Range ADC
In applications where jitter is critical, such as when digitiz-
ing high input frequencies, use as large an amplitude as
possible. Also, if the ADC is clocked with a sinusoidal
signal, filter the CLK signal to reduce wideband noise and
distortion products generated by the source.
Figures 12 and 13 show alternatives for converting a
differential clock to the single-ended CLK input. The use of
Input Range
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise perfor-
mance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 0.9dB.
Driving the Clock Input
The CLK input can be driven directly with a CMOS or TTL
level signal. A sinusoidal clock can also be used along with
a low-jitter squaring circuit before the CLK pin (see
Figure 11).
The noise performance of the LTC2251/LTC2250 can
depend on the clock signal quality as much as on the
analog input. Any noise present on the clock signal will
result in additional aperture jitter that will be RMS summed
with the inherent ADC aperture jitter.
Figure 11. Sinusoidal Single-Ended CLK Drive
CLK
50
0.1
F
0.1
F
4.7
F
1k
FERRITE
BEAD
CLEAN
SUPPLY
SINUSOIDAL
CLOCK
INPUT
22510 F11
NC7SVU04
LTC2251/
LTC2250
CLK
100
0.1
F
4.7
F
FERRITE
BEAD
CLEAN
SUPPLY
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
22510 F12
LTC2251/
LTC2250
CLK
5pF-30pF
ETC1-1T
0.1
F
VCM
FERRITE
BEAD
DIFFERENTIAL
CLOCK
INPUT
22510 F13
LTC2251/
LTC2250
Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter
Figure 13. LVDS or PECL CLK Drive Using a Transformer
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