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参数资料
| 型号： | LTC2254IUH#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 10/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 105MSPS 3V 32-QFN |
| 标准包装： | 2,500 |
| 位数： | 14 |
| 采样率（每秒）： | 105M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 378mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个单端，双极; 1 个差分，双极 |
LTC2255/LTC2254
18
22554fa
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2255/LTC2254 should drive a
minimal capacitive load to avoid possible interaction be-
tween the digital outputs and sensitive input circuitry. For
full speed operation the capacitive load should be kept
under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Data Format
Using the MODE pin, the LTC2255/LTC2254 parallel
digital output can be selected for offset binary or 2’s
complement format. Connecting MODE to GND or 1/3VDD
selects offset binary output format. Connecting MODE to
2/3VDD or VDD selects 2’s complement output format. An
external resistor divider can be used to set the 1/3VDD or
2/3VDD logic values. Table 2 shows the logic states for the
MODE pin.
to 1V and must be less than OVDD. The logic outputs will
swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF. The data
access and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed
operation. The output Hi-Z state is intended for use during
long periods of inactivity.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to VDD and OE to VDD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to VDD and OE
to GND results in nap mode, which typically dissipates
15mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Grounding and Bypassing
The LTC2255/LTC2254 requires a printed circuit board
with a clean, unbroken ground plane. A multilayer board
with an internal ground plane is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, REFH, and REFL pins. Bypass
capacitors must be located as close to the pins as pos-
sible. Of particular importance is the 0.1
F capacitor
between REFH and REFL. This capacitor should be placed
as close to the device as possible (1.5mm or less). A size
0402 ceramic capacitor is recommended. The large 2.2
F
capacitor between REFH and REFL can be somewhat
Table 2. MODE Pin Function
Clock Duty
MODE Pin
Output Format
Cycle Stablizer
0
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply, then OVDD should be tied to that same 1.8V supply.
OVDD can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND up
APPLICATIO S I FOR ATIO
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2255 | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 125/105Msps Low Power 3V ADCs |
| LTC2255CUH | 制造商:Linear Technology 功能描述:ADC Single Pipelined 125Msps 14-bit Parallel 32-Pin QFN EP |
| LTC2255CUH#PBF | 功能描述:IC ADC 14-BIT 125MSPS 3V 32-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
| LTC2255CUH#TRPBF | 功能描述:IC ADC 14BIT 125MSPS 3V 32-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:12 采样率（每秒）:3M 数据接口:- 转换器数目:- 功率耗散（最大）:- 电压电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:SOT-23-6 供应商设备封装:SOT-23-6 包装:带卷 (TR) 输入数目和类型:- |
| LTC2255IUH | 制造商:Linear Technology 功能描述:ADC Single Pipelined 125Msps 14-bit Parallel 32-Pin QFN EP |
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