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参数资料
| 型号： | LTC2255CUH#TR |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 14-Bit, 125Msps Low Power 3V ADCs; Package: QFN; No of Pins: 32; Temperature Range: 0°C to +70°C |
| 中文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC32 |
| 封装： | 5 X 5 MM, PLASTIC, MO-220-WHHD, QFN-32 |
| 文件页数： | 10/24页 |
| 文件大小： | 620K |
| 代理商： | LTC2255CUH#TR |
LTC2255/LTC2254
18
22554fa
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2255/LTC2254 should drive a
minimal capacitive load to avoid possible interaction be-
tween the digital outputs and sensitive input circuitry. For
full speed operation the capacitive load should be kept
under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Data Format
Using the MODE pin, the LTC2255/LTC2254 parallel
digital output can be selected for offset binary or 2’s
complement format. Connecting MODE to GND or 1/3VDD
selects offset binary output format. Connecting MODE to
2/3VDD or VDD selects 2’s complement output format. An
external resistor divider can be used to set the 1/3VDD or
2/3VDD logic values. Table 2 shows the logic states for the
MODE pin.
to 1V and must be less than OVDD. The logic outputs will
swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF. The data
access and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed
operation. The output Hi-Z state is intended for use during
long periods of inactivity.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to VDD and OE to VDD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to VDD and OE
to GND results in nap mode, which typically dissipates
15mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Grounding and Bypassing
The LTC2255/LTC2254 requires a printed circuit board
with a clean, unbroken ground plane. A multilayer board
with an internal ground plane is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, REFH, and REFL pins. Bypass
capacitors must be located as close to the pins as pos-
sible. Of particular importance is the 0.1
F capacitor
between REFH and REFL. This capacitor should be placed
as close to the device as possible (1.5mm or less). A size
0402 ceramic capacitor is recommended. The large 2.2
F
capacitor between REFH and REFL can be somewhat
Table 2. MODE Pin Function
Clock Duty
MODE Pin
Output Format
Cycle Stablizer
0
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply, then OVDD should be tied to that same 1.8V supply.
OVDD can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND up
APPLICATIO S I FOR ATIO
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