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| 型号： | LTC2255IUH#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 5/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 125MSPS 3V 32-QFN |
| 产品培训模块： | LTC2262 - Ultra Low Power High Speed ADCs |
| 标准包装： | 2,500 |
| 位数： | 14 |
| 采样率（每秒）： | 125M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 468mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个单端，双极; 1 个差分，双极 |
LTC2255/LTC2254
13
22554fa
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H during
this high phase of CLK. When CLK goes back low, the first
stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When CLK goes back high,
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
third, fourth and fifth stages, resulting in a fifth stage
residue that is sent to the sixth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2255/
LTC2254 CMOS differential sample-and-hold. The analog
inputs are connected to the sampling capacitors (CSAMPLE)
through NMOS transistors. The capacitors shown at-
tached to each input (CPARASITIC) are the summation of all
other capacitance associated with each input.
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage.
When CLK transitions from low to high, the sampled input
voltage is held on the sampling capacitors. During the hold
phase when CLK is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
APPLICATIO S I FOR ATIO
WU
U
to the ADC core for processing. As CLK transitions from
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
Figure 2. Equivalent Input Circuit
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, AIN+
should be driven with the input signal and AIN– should be
connected to 1.5V or VCM.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing
±0.5V for
the 2V range or
±0.25V for the 1V range, around a
common mode voltage of 1.5V. The VCM output pin (Pin
31) may be used to provide the common mode bias level.
VCM can be tied directly to the center tap of a transformer
to set the DC input level or as a reference level to an op amp
differential driver circuit. The VCM pin must be bypassed to
ground close to the ADC with a 2.2
F or greater capacitor.
VDD
15
15
CPARASITIC
1pF
CPARASITIC
1pF
CSAMPLE
3.5pF
CSAMPLE
3.5pF
LTC2255/LTC2254
AIN+
AIN–
CLK
22554 F02
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2256-12 | 制造商:LINER 制造商全称:Linear Technology 功能描述:12-Bit, 65/40/2 5Msps Ultralow Power 1.8V ADCs |
| LTC2256-14 | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 65/40/25Msps Ultralow Power 1.8V ADCs |
| LTC2256CUJ-12#PBF | 功能描述:IC ADC 12BIT 25MSPS 1.8V 40-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
| LTC2256CUJ-12#TRPBF | 功能描述:IC ADC 12BIT 25MSPS 1.8V 40-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
| LTC2256CUJ-12-PBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:12-Bit, 65/40/2 5Msps Ultralow Power 1.8V ADCs |
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