参数资料
型号: LTC2262CUJ-12#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: ADC
英文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
封装: 6 X 6 MM, LEAD FREE, PLASTIC, QFN-40
文件页数: 10/28页
文件大小: 481K
代理商: LTC2262CUJ-12#PBF
LTC2262-12
18
226212fa
Overow Bit
The overow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged.
The overow bit has the same pipeline latency as the
data bits.
Phase Shifting the Output Clock
In full-rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT+,
so the rising edge of CLKOUT+ can be used to latch the
output data. In double data rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT+. To allow adequate
setup-and-hold time when latching the data, the CLKOUT+
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
The LTC2262-12 can also phase shift the CLKOUT+/
CLKOUTsignals by serially programming mode con-
trol register A2. The output clock can be shifted by
0°, 45°, 90° or 135°. To use the phase shifting feature
the clock duty cycle stabilizer must be turned on.
Another control register bit can invert the polarity of
CLKOUT+ and CLKOUT, independently of the phase shift.
The combination of these two features enables phase
shifts of 45° up to 315° (Figure 14).
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V RANGE)
OF
D11-D0
(OFFSET BINARY)
D11-D0
(2’s COMPLEMENT)
>+1.000000V
+0.999512V
+0.999024V
1
0
1111 1111 1111
1111 1111 1110
0111 1111 1111
0111 1111 1110
+0.000488V
0.000000V
–0.000488V
–0.000976V
0
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
–0.999512V
–1.000000V
≤–1.000000V
0
1
0000 0000 0001
0000 0000 0000
1000 0000 0001
1000 0000 0000
APPLICATIONS INFORMATION
CLKOUT+
D0-D11, OF
PHASE
SHIFT
45°
90°
135°
180°
225°
270°
315°
CLKINV
0
1
CLKPHASE1
MODE CONTROL BITS
0
1
0
1
CLKPHASE0
0
1
0
1
0
1
0
1
226212 F14
ENC+
Figure 14. Phase Shifting CLKOUT
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