参数资料
型号: LTC2262IUJ-12#TRPBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: ADC
英文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
封装: 6 X 6 MM, LEAD FREE, PLASTIC, QFN-40
文件页数: 5/28页
文件大小: 481K
代理商: LTC2262IUJ-12#TRPBF
LTC2262-12
13
226212fa
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
DIFF
REF
AMP
REF
BUF
2.2μF
0.1μF
INTERNAL CLOCK SIGNALS
REFH
REFL
CLOCK/DUTY
CYCLE
CONTROL
RANGE
SELECT
1.25V
REFERENCE
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
ENC+
ENC
SHIFT REGISTER
AND CORRECTION
SDO
CS
OGND
OF
OVDD
D11
CLKOUT
CLKOUT+
D0
226212 F01
INPUT
S/H
SENSE
VREF
AIN
AIN
+
1μF
VCM
0.1μF
VDD/2
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
MODE
CONTROL
REGISTERS
SCK
PAR/SER
SDI
VDD
GND
APPLICATIONS INFORMATION
Figure 2. Equivalent Input Circuit
CSAMPLE
3.5pF
RON
25Ω
RON
25Ω
VDD
LTC2262-12
AIN
+
226212 F02
CSAMPLE
3.5pF
VDD
AIN
ENC
ENC+
1.2V
10k
1.2V
10k
CPARASITIC
1.8pF
CPARASITIC
1.8pF
10Ω
CONVERTER OPERATION
The LTC2262-12 is a low power 12-bit 150Msps A/D
converter that is powered by a single 1.8V supply. The
analog inputs should be driven differentially. The encode
input can be driven differentially or single-ended for lower
power consumption. The digital outputs can be CMOS,
double data rate CMOS (to halve the number of output
lines), or double data rate LVDS (to reduce digital noise in
the system.) Many additional features can be chosen by
programming the mode control registers through a serial
SPI port. See the Serial Programming Mode section.
ANALOG INPUT
The analog input is a differential CMOS sample-and-hold
circuit (Figure 2). The inputs should be driven differentially
around a common mode voltage set by the VCM output
相关PDF资料
PDF描述
LTC2262CUJ-12#PBF 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
LTC2264CUJ-14#TRPBF PROPRIETARY METHOD ADC, QCC40
LTC2265CUJ-14#PBF PROPRIETARY METHOD ADC, QCC40
LTC2263CUJ-14#PBF PROPRIETARY METHOD ADC, QCC40
LTC2263CUJ-14#TRPBF PROPRIETARY METHOD ADC, QCC40
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