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参数资料
| 型号： | LTC2263IUJ-12#TRPBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | PROPRIETARY METHOD ADC, QCC40 |
| 封装： | 6 X 6 MM, LEAD FREE, PLASTIC, QFN-40 |
| 文件页数： | 16/34页 |
| 文件大小： | 1231K |
| 代理商： | LTC2263IUJ-12#TRPBF |
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LTC2265-12/
LTC2264-12/LTC2263-12
23
22654312fb
APPLICATIONS INFORMATION
The differential encode mode is recommended for sinu-
soidal, PECL, or LVDS encode inputs (Figures 12 and 13).
The encode inputs are internally biased to 1.2V through
10k equivalent resistance. The encode inputs can be taken
above VDD (up to 3.6V), and the common mode range
is from 1.1V to 1.6V. In the differential encode mode,
ENC– should stay at least 200mV above ground to avoid
falsely triggering the single-ended encode mode. For
good jitter performance ENC+ should have fast rise and
fall times.
The single-ended encode mode should be used with
CMOS encode inputs. To select this mode, ENC– is con-
nected to ground and ENC+ is driven with a square wave
encode input. ENC+ can be taken above VDD (up to 3.6V)
so 1.8V to 3.3V CMOS logic levels can be used. The
ENC+ threshold is 0.9V. For good jitter performance
ENC+ should have fast rise and fall times.
Clock PLL and Duty Cycle Stabilizer
The encode clock is multiplied by an internal phase-locked
loop (PLL) to generate the serial digital output data. If the
encode signal changes frequency or is turned off, the PLL
requires 25s to lock onto the input clock.
A clock duty cycle stabilizer circuit allows the duty cycle
of the applied encode signal to vary from 30% to 70%.
In the serial programming mode it is possible to disable
the duty cycle stabilizer, but this is not recommended. In
the parallel programming mode the duty cycle stabilizer
is always enabled.
DIGITAL OUTPUTS
The digital outputs of the LTC2265-12/LTC2264-12/
LTC2263-12 are serialized LVDS signals. Each channel
outputs two bits at a time (2-lane mode) or one bit at a
time (1-lane mode). The data can be serialized with 16-,
14-, or 12-bit serialization (see the Timing Diagrams sec-
tion for details).
The output data should be latched on the rising and falling
edges of the data clockout (DCO). A data frame output
(FR) can be used to determine when the data from a new
conversion result begins. In the 2-lane, 14-bit serialization
mode, the frequency of the FR output is halved.
The maximum serial data rate for the data outputs is
1Gbps, so the maximum sample rate of the ADC will de-
pend on the serialization mode as well as the speed grade
of the ADC (see Table 1). The minimum sample rate for
all serialization modes is 5Msps.
50
100
0.1F
T1
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
50
LTC2265-12
226512 F12
ENC–
ENC+
ENC+
ENC–
PECL OR
LVDS
CLOCK
0.1F
226512 F13
LTC2265-12
Figure 12. Sinusoidal Encode Drive
Figure 13. PECL or LVDS Encode Drive
相关PDF资料 |
PDF描述 |
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| LTC2265CUJ-12#PBF | PROPRIETARY METHOD ADC, QCC40 |
| LTC2263IUJ-12#PBF | PROPRIETARY METHOD ADC, QCC40 |
| LTC2264IUJ-12#TRPBF | PROPRIETARY METHOD ADC, QCC40 |
| LTC2272CUJ#TR | 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40 |
| LTC2272IUJ | 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2263IUJ-14 | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 65Msps/40Msps/25Msps Low Power Dual ADCs |
| LTC2263IUJ-14#PBF | 功能描述:IC ADC 14BIT SER/PAR 25M 40-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
| LTC2263IUJ-14#TRPBF | 功能描述:IC ADC 14BIT SER/PAR 25M 40-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| LTC2263IUJ-14PBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 65Msps/40Msps/25Msps Low Power Dual ADCs |
| LTC2263IUJ-14TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 65Msps/40Msps/25Msps Low Power Dual ADCs |
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