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参数资料
| 型号： | LTC2265CUJ-14#TRPBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | PROPRIETARY METHOD ADC, QCC40 |
| 封装： | 6 X 6 MM, LEAD FREE, PLASTIC, QFN-40 |
| 文件页数： | 16/32页 |
| 文件大小： | 1451K |
| 代理商： | LTC2265CUJ-14#TRPBF |
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LTC2265-14/
LTC2264-14/LTC2263-14
23
22654314fb
APPLICATIONS INFORMATION
The digital output is randomized by applying an exclu-
sive-OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is
applied—an exclusive-OR operation is applied between
the LSB and all other bits. The FR and DCO outputs are
not affected. The output randomizer is enabled by serially
programming mode control register A1.
Digital Output Test Pattern
To allow in-circuit testing of the digital interface to the
A/D, there is a test mode that forces the A/D data outputs
(D13-D0) of all channels to known values. The digital
output test patterns are enabled by serially programming
mode control registers A3 and A4. When enabled, the
test patterns override all other formatting modes: 2’s
complement and randomizer.
Output Disable
Thedigitaloutputsmaybedisabledbyseriallyprogramming
mode control register A2. The current drive for all digital
outputs, including DCO and FR, are disabled to save power
or enable in-circuit testing. When disabled, the common
mode of each output pair becomes high impedance, but
the differential impedance may remain low.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire chip is powered down,
resulting in 1mW power consumption. Sleep mode is
enabled by mode control register A1 (serial program-
ming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on VREF,
REFH and REFL. For the suggested values in Figure 8, the
A/D will stabilize after 2ms.
In nap mode any combination of A/D channels can be
powered down while the internal reference circuits and the
PLL stay active, allowing faster wake-up than from sleep
mode. Recovering from nap mode requires at least 100
clockcycles.IftheapplicationdemandsaveryaccurateDC
settling, then an additional 50s should be allowed so the
on-chip references can settle from the slight temperature
shift caused by the change in supply current as the A/D
leavesnapmode.Napmodeisenabledbythemodecontrol
register A1 in the serial programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2265-14/LTC2264-14/
LTC2263-14 can be programmed by either a parallel
interface or a simple serial interface. The serial interface
has more flexibility and can program all available modes.
Theparallelinterfaceismorelimitedandcanonlyprogram
some of the more commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK, SDI and SDO pins are binary
logic inputs that set certain operating modes. These pins
can be tied to VDD or ground, or driven by 1.8V, 2.5V or
3.3V CMOS logic. When used as an input, SDO should
be driven through a 1k series resistor. Table 3 shows the
modes set by CS, SCK, SDI and SDO.
Table 3. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN
DESCRIPTION
CS
2-Lane/1-Lane Selection Bit
0 = 2-Lane, 16-Bit Serialization Output Mode
1 = 1-Lane, 14-Bit Serialization Output Mode
SCK
LVDS Current Selection Bit
0 = 3.5mA LVDS Current Mode
1 = 1.75mA LVDS Current Mode
SDI
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode
SDO
Internal Termination Selection Bit
0 = Internal Termination Disabled
1 = Internal Termination Enabled
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D mode control
registers. Data is written to a register with a 16-bit serial
word. Data can also be read back from a register to verify
its contents.
相关PDF资料 |
PDF描述 |
|---|---|
| LTC2265IUJ-14#PBF | PROPRIETARY METHOD ADC, QCC40 |
| LTC2265IUJ-12#PBF | PROPRIETARY METHOD ADC, QCC40 |
| LTC2265CUJ-12#TRPBF | PROPRIETARY METHOD ADC, QCC40 |
| LTC2263CUJ-12#PBF | PROPRIETARY METHOD ADC, QCC40 |
| LTC2264CUJ-12#TRPBF | PROPRIETARY METHOD ADC, QCC40 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2265IUJ-12#PBF | 功能描述:IC ADC 12BIT SER/PAR 65M 40-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
| LTC2265IUJ-12#TRPBF | 功能描述:IC ADC 12BIT SER/PAR 65M 40-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| LTC2265IUJ-12PBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:12-Bit, 65Msps/40Msps/25Msps Low Power Dual ADCs |
| LTC2265IUJ-12TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:12-Bit, 65Msps/40Msps/25Msps Low Power Dual ADCs |
| LTC2265IUJ-14 | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 65Msps/40Msps/25Msps Low Power Dual ADCs |
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