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参数资料
| 型号： | LTC2281CUP#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 11/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL 10BIT 125MSPS 64QFN |
| 标准包装： | 40 |
| 位数： | 10 |
| 采样率（每秒）： | 125M |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 915mW |
| 电压电源： | 单电源 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-WFQFN 裸露焊盘 |
| 供应商设备封装： | 64-QFN（9x9） |
| 包装： | 管件 |
| 输入数目和类型： | 2 个单端，双极; 2 个差分, 双极 |
| 产品目录页面： | 1349 (CN2011-ZH PDF) |
LTC2281
19
2281fb
APPLICATIONS INFORMATION
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capaci-
tors must be located as close to the pins as possible. Of
particular importance is the 0.1μF capacitor between REFH
and REFL. This capacitor should be placed as close to the
device as possible (1.5mm or less). A size 0402 ceramic
capacitor is recommended. The large 2.2μF capacitor be-
tween REFH and REFL can be somewhat further away. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
The LTC2281 differential inputs should run parallel and
close to each other. The input traces should be as short
as possible to minimize capacitance and to minimize
noise pickup.
Heat Transfer
Most of the heat generated by the LTC2281 is transferred
from the die through the bottom-side Exposed Pad and
package leads onto the printed circuit board. For good
electrical and thermal performance, the Exposed Pad
should be soldered to a large grounded pad on the PC
board. It is critical that all ground pins are connected to
a ground plane of sufcient area.
Clock Sources for Undersampling
Undersampling is especially demanding on the clock
source, and the higher the input frequency, the greater the
sensitivity to clock jitter or phase noise. A clock source that
degrades SNR of a full-scale signal by 1dB at 70MHz will
degrade SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
In cases where absolute clock frequency accuracy is
relatively unimportant and only a single ADC is required,
a 3V canned oscillator from vendors such as Saronix
or Vectron can be placed close to the ADC and simply
connected directly to the ADC. If there is any distance to
the ADC, some source termination to reduce ringing that
may occur even over a fraction of an inch is advisable.
You must not allow the clock to overshoot the supplies or
performance will suffer. Do not lter the clock signal with
a narrow band lter unless you have a sinusoidal clock
source, as the rise and fall time artifacts present in typical
digital clock signals will be translated into phase noise.
The lowest phase noise oscillators have single-ended
sinusoidal outputs, and for these devices the use of a lter
close to the ADC may be benecial. This lter should be
close to the ADC to both reduce roundtrip reection times,
as well as reduce the susceptibility of the traces between
the lter and the ADC. If the circuit is sensitive to close-
in phase noise, the power supply for oscillators and any
buffers must be very stable, or propagation delay variation
with supply will translate into phase noise. Even though
these clock sources may be regarded as digital devices, do
not operate them on a digital supply. If your clock is also
used to drive digital devices such as an FPGA, you should
locate the oscillator, and any clock fan-out devices close to
the ADC, and give the routing to the ADC precedence. The
clock signals to the FPGA should have series termination at
the driver to prevent high frequency noise from the FPGA
disturbing the substrate of the clock fan-out device. If you
use an FPGA as a programmable divider, you must re-time
the signal using the original oscillator, and the re-timing
ip-op as well as the oscillator should be close to the
ADC, and powered with a very quiet supply.
For cases where there are multiple ADCs, or where the
clock source originates some distance away, differential
clock distribution is advisable. This is advisable both from
the perspective of EMI, but also to avoid receiving noise
from digital sources both radiated, as well as propagated in
the waveguides that exist between the layers of multilayer
PCBs. The differential pairs must be close together and
distanced from other signals. The differential pair should
be guarded on both sides with copper distanced at least
3x the distance between the traces, and grounded with
vias no more than 1/4 inch apart.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2281CUP-TR | 制造商:LINER 制造商全称:Linear Technology 功能描述:Dual 10-Bit, 125Msps Low Power 3V ADC |
| LTC2281CUP-TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:Dual 10-Bit, 125Msps Low Power 3V ADC |
| LTC2281IUP | 制造商:LINER 制造商全称:Linear Technology 功能描述:Dual 10-Bit, 125Msps Low Power 3V ADC |
| LTC2281IUP#PBF | 功能描述:IC ADC 10BIT DUAL 64-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| LTC2281IUP#TRPBF | 功能描述:IC ADC DUAL 10BIT 125MSPS 64QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
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