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参数资料
| 型号： | LTC2285IUP#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 23/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL 14BIT 125MSPS 64QFN |
| 标准包装： | 40 |
| 位数： | 14 |
| 采样率（每秒）： | 125M |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 915mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-WFQFN 裸露焊盘 |
| 供应商设备封装： | 64-QFN（9x9） |
| 包装： | 管件 |
| 输入数目和类型： | 2 个单端，双极; 2 个差分, 双极 |
LTC2285
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PIN FUNCTIONS
AINA+ (Pin 1): Channel A Positive Differential Analog
Input.
AINA– (Pin 2): Channel A Negative Differential Analog
Input.
REFHA (Pins 3, 4): Channel A High Reference. Short to-
gether and bypass to Pins 5, 6 with a 0.1μF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 5, 6 with an additional 2.2μF ceramic chip capacitor
and to ground with a 1μF ceramic chip capacitor.
REFLA (Pins 5, 6): Channel A Low Reference. Short to-
gether and bypass to Pins 3, 4 with a 0.1μF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 3, 4 with an additional 2.2μF ceramic chip capacitor
and to ground with a 1μF ceramic chip capacitor.
VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to
GND with 0.1μF ceramic chip capacitors.
CLKA (Pin 8): Channel A Clock Input. The input sample
starts on the positive edge.
CLKB (Pin 9): Channel B Clock Input. The input sample
starts on the positive edge.
REFLB (Pins 11, 12): Channel B Low Reference. Short
together and bypass to Pins 13, 14 with a 0.1μF ceramic
chip capacitor as close to the pin as possible. Also by-
pass to Pins 13, 14 with an additional 2.2μF ceramic
chip capacitor and to ground with a 1μF ceramic chip
capacitor.
REFHB (Pins 13, 14): Channel B High Reference. Short
together and bypass to Pins 11, 12 with a 0.1μF ceramic
chip capacitor as close to the pin as possible. Also by-
pass to Pins 11, 12 with an additional 2.2μF ceramic
chip capacitor and to ground with a 1μF ceramic chip
capacitor.
AINB– (Pin 15): Channel B Negative Differential Analog
Input.
AINB+ (Pin 16): Channel B Positive Differential Analog
Input.
GND (Pins 17, 64): ADC Power Ground.
SENSEB (Pin 19): Channel B Reference Programming Pin.
Connecting SENSEB to VCMB selects the internal reference
and a ±0.5V input range. VDD selects the internal reference
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEB selects an input
range of ±VSENSEB. ±1V is the largest valid input range.
VCMB (Pin 20): Channel B 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2μF ceramic chip
capacitor. Do not connect to VCMA.
MUX (Pin 21): Digital Output Multiplexer Control. If MUX
is High, Channel A comes out on DA0-DA13; Channel B
comes out on DB0-DB13. If MUX is Low, the output bus-
ses are swapped and Channel A comes out on DB0-DB13;
Channel B comes out on DA0-DA13. To multiplex both
channels onto a single output bus, connect MUX, CLKA
and CLKB together. (This is not recommended at clock
frequencies above 80Msps.)
SHDNB (Pin 22): Channel B Shutdown Mode Selection
Pin. Connecting SHDNB to GND and OEB to GND results
in normal operation with the outputs enabled. Connecting
SHDNB to GND and OEB to VDD results in normal operation
with the outputs at high impedance. Connecting SHDNB
to VDD and OEB to GND results in nap mode with the
outputs at high impedance. Connecting SHDNB to VDD
and OEB to VDD results in sleep mode with the outputs
at high impedance.
OEB (Pin 23): Channel B Output Enable Pin. Refer to
SHDNB pin function.
DB0 – DB13 (Pins 24 to 30, 33 to 39): Channel B Digital
Outputs. DB13 is the MSB.
OGND (Pins 31, 50): Output Driver Ground.
OVDD (Pins 32, 49): Positive Supply for the Output Drivers.
Bypass to ground with 0.1μF ceramic chip capacitor.
CLKOUT (Pin 40): Data Ready Clock Output. Latch data
on the falling edge of CLKOUT. CLKOUT is derived from
CLKB. Tie CLKA to CLKB for simultaneous operation.
DA0 – DA13 (Pins 41 to 48, 51 to 56): Channel A Digital
Outputs. DA13 is the MSB.
OF (Pin 57): Overow/Underow Output. High when an
overow or underow has occurred on either channel A
or channel B.
OEA (Pin 58): Channel A Output Enable Pin. Refer to
SHDNA pin function.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2285IUP-TR | 制造商:LINER 制造商全称:Linear Technology 功能描述:Dual 14-Bit, 125Msps Low Power 3V ADC |
| LTC2285IUP-TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:Dual 14-Bit, 125Msps Low Power 3V ADC |
| LTC2285UP | 制造商:LINER 制造商全称:Linear Technology 功能描述:Dual 14-Bit, 135Msps Low Power 3.3V ADC |
| LTC2286 | 制造商:LINER 制造商全称:Linear Technology 功能描述:Dual 10-Bit, 65/40/25Msps Low Noise 3V ADCs |
| LTC2286CUP | 制造商:LINER 制造商全称:Linear Technology 功能描述:Dual 10-Bit, 65/40/25Msps Low Noise 3V ADCs |
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