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参数资料
| 型号： | LTC2299IUP#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 23/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL 14BIT 80MSPS 64QFN |
| 标准包装： | 2,000 |
| 位数： | 14 |
| 采样率（每秒）： | 80M |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 516mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-WFQFN 裸露焊盘 |
| 供应商设备封装： | 64-QFN（9x9） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，双极; 2 个差分, 双极 |
LTC2299
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AINA+ (Pin 1): Channel A Positive Differential Analog
Input.
AINA– (Pin 2): Channel A Negative Differential Analog
Input.
REFHA (Pins 3, 4): Channel A High Reference. Short
together and bypass to Pins 5, 6 with a 0.1
F ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 5, 6 with an additional 2.2
F ceramic chip capacitor
and to ground with a 1
F ceramic chip capacitor.
REFLA (Pins 5, 6): Channel A Low Reference. Short
together and bypass to Pins 3, 4 with a 0.1
F ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 3, 4 with an additional 2.2
F ceramic chip capacitor
and to ground with a 1
F ceramic chip capacitor.
VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to
GND with 0.1
F ceramic chip capacitors.
CLKA (Pin 8): Channel A Clock Input. The input sample
starts on the positive edge.
CLKB (Pin 9): Channel B Clock Input. The input sample
starts on the positive edge.
REFLB (Pins 11, 12): Channel B Low Reference. Short
together and bypass to Pins 13, 14 with a 0.1
F ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 13, 14 with an additional 2.2
F ceramic chip ca-
pacitor and to ground with a 1
F ceramic chip capacitor.
REFHB (Pins 13, 14): Channel B High Reference. Short
together and bypass to Pins 11, 12 with a 0.1
F ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 11, 12 with an additional 2.2
F ceramic chip ca-
pacitor and to ground with a 1
F ceramic chip capacitor.
AINB– (Pin 15): Channel B Negative Differential Analog
Input.
AINB+ (Pin 16): Channel B Positive Differential Analog
Input.
GND (Pins 17, 64): ADC Power Ground.
SENSEB (Pin 19): Channel B Reference Programming Pin.
Connecting SENSEB to VCMB selects the internal reference
and a
±0.5V input range. VDD selects the internal reference
and a
±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEB selects an input
range of
±VSENSEB. ±1V is the largest valid input range.
VCMB (Pin 20): Channel B 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2
F ceramic chip
capacitor. Do not connect to VCMA.
MUX (Pin 21): Digital Output Multiplexer Control. If MUX
is High, Channel A comes out on DA0-DA13, OFA; Channel B
comes out on DB0-DB13, OFB. If MUX is Low, the output
busses are swapped and Channel A comes out on DB0-
DB13, OFB; Channel B comes out on DA0-DA13, OFA. To
multiplex both channels onto a single output bus, connect
MUX, CLKA and CLKB together.
SHDNB (Pin 22): Channel B Shutdown Mode Selection
Pin. Connecting SHDNB to GND and OEB to GND results
in normal operation with the outputs enabled. Connecting
SHDNB to GND and OEB to VDD results in normal opera-
tion with the outputs at high impedance. Connecting
SHDNB to VDD and OEB to GND results in nap mode with
the outputs at high impedance. Connecting SHDNB to VDD
and OEB to VDD results in sleep mode with the outputs at
high impedance.
OEB (Pin 23): Channel B Output Enable Pin. Refer to
SHDNB pin function.
DB0 – DB13 (Pins 24 to 30, 33 to 39): Channel B Digital
Outputs. DB13 is the MSB.
OGND (Pins 31, 50): Output Driver Ground.
OVDD (Pins 32, 49): Positive Supply for the Output Driv-
ers. Bypass to ground with 0.1
F ceramic chip capacitor.
OFB (Pin 40): Channel B Overflow/Underflow Output.
High when an overflow or underflow has occurred.
DA0 – DA13 (Pins 41 to 48, 51 to 56): Channel A Digital
Outputs. DA13 is the MSB.
OFA (Pin 57): Channel A Overflow/Underflow Output.
High when an overflow or underflow has occurred.
OEA (Pin 58): Channel A Output Enable Pin. Refer to
SHDNA pin function.
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