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参数资料
| 型号： | LTC2301HMS#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO12 |
| 封装： | LEAD FREE, PLASTIC, MSOP-12 |
| 文件页数： | 8/26页 |
| 文件大小： | 881K |
| 代理商： | LTC2301HMS#PBF |
LTC2301/LTC2305
16
23015fb
APPLICATIONS INFORMATION
Internal Conversion Clock
The internal conversion clock is factory trimmed to
achieve a typical conversion time (tCONV) of 1.3μs and a
maximum conversion time of 1.6μs over the full operating
temperature range.
I2C Interface
The LTC2301/LTC2305 communicate through an I2C in-
terface. The I2C interface is a 2-wire open-drain interface
supporting multiple devices and multiple masters on a
single bus. The connected devices can only pull the serial
data line (SDA) LOW and can never drive it HIGH. SDA is
required to be externally connected to the supply through
a pull-up resistor. When the data line is not being driven
low, it is HIGH. Data on the I2C bus can be transferred at
rates up to 100kbits/s in the standard mode and up to
400kbits/s in the fast mode.
The VDD power should not be removed from the LTC2301/
LTC2305 when the I2C bus is active to avoid loading the I2C
bus lines through the internal ESD protection diodes.
Each device on the I2C bus is recognized by a unique
address stored in the device and can only operate either
as a transmitter or receiver, depending on the function of
the device. A device can also be considered as a master
or a slave when performing data transfers. A master is
the device which initiates a data transfer on the bus and
generates the clock signals to permit the transfer. Devices
addressed by the master are considered slaves.
The LTC2301/LTC2305 can only be addressed as slaves.
Once addressed, they can receive conguration bits (DIN
word) or transmit the last conversion result. The serial clock
line (SCL) is always an input to the LTC2301/LTC2305 and
the serial data line (SDA) is bidirectional. These devices
support the standard mode and the fast mode for data
transfer speeds up to 400kbits/s (see Timing Diagram
section for denition of the I2C timing).
The START and STOP Conditions
Referring to Figure 6, a START (S) condition is generated
by transitioning SDA from HIGH to LOW while SCL is
HIGH. The bus is considered to be busy after the START
condition. When the data transfer is nished, a STOP (P)
condition is generated by transitioning SDA from LOW
to HIGH while SCL is HIGH. The bus is free after a STOP
condition is generated. START and STOP conditions are
always generated by the master.
When the bus is in use, it stays busy if a repeated START
(Sr) is generated instead of a STOP condition. The repeated
START timing is functionally identical to the START and is
used for writing and reading from the device before the
initiation of a new conversion.
Data Transferring
After the START condition, the I2C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit. The
master releases the SDA line during the ninth SCL clock
cycle. The slave device can issue an ACK by pulling SDA
LOW or issue a Not Acknowledge (NACK) by leaving the
SDA line high impedance (the external pull-up resistor will
hold the line HIGH). Change of data only occurs while the
SCL line is LOW.
Data Format
After a START condition, the master sends a 7-bit ad-
dress followed by a read/write (R/W) bit. The R/W bit is
1 for a read request and 0 for a write request. If the 7-bit
address matches one of the LTC2301/LTC2305’s 9 pin-
selectable addresses (see Table 2), the ADC is selected.
When the ADC is addressed during a conversion, it will
not acknowledge R/W requests and will issue a NACK by
leaving the SDA line HIGH. If the conversion is complete,
the LTC2301/LTC2305 issues an ACK by pulling the SDA
line LOW. The LTC2301/LTC2305 has two registers. The
12-bit wide output register contains the last conversion
result. The 6-bit wide input register congures the input
MUX and the operating mode of the ADC.
Figure 6. Timing Diagrams of START and STOP Conditions
S
START Condition
STOP Condition
P
23015 F06
SDA
SCL
SDA
SCL
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