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| 型号： | LTC2351HUH-12#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 6-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC32 |
| 封装： | 5 X 5 MM, LEAD FREE, PLASTIC, MO-220WHHD, QFN-32 |
| 文件页数： | 10/20页 |
| 文件大小： | 224K |
| 代理商： | LTC2351HUH-12#PBF |
LTC2351-12
18
235112fa
APPLICATIONS INFORMATION
the rising edge of CONV. The six or fewer 12-bit words are
separated by two don’t care bits and two clock cycles in
high impedance mode. Please note the delay specication
from SCK to a valid SDO. SDO is always guaranteed to
be valid by the next rising edge of SCK. The 16 – 96-bit
output data stream is compatible with the 16-bit or 32-bit
serial port of most processors.
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC2351-12, a printed circuit board
with ground plane is required. Layout for the printed circuit
board should ensure that digital and analog signal lines
are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track. If optimum phase match between the
inputs is desired, the length of the twelve input wires of
the six input channels should be kept matched. But each
pair of input wires to the six input channels should be
kept separated by a ground trace to avoid high frequency
crosstalk between channels.
High quality tantalum and ceramic bypass capacitors
should be used at the VCC, VDD and VREF pins as shown
in the Block Diagram on the rst page of this data sheet.
For optimum performance, a 10μF surface mount tantalum
capacitor with a 0.1μF ceramic is recommended for the
VCC, VDD and VREF pins. Alternatively, 10μF ceramic chip
capacitors such as X5R or X7R may be used. The capaci-
tors must be located as close to the pins as possible. The
traces connecting the pins and the bypass capacitors must
be kept short and should be made as wide as possible. The
VCC and VDD bypass capacitor returns to the ground plane
and the VREF bypass capacitor returns to the Pin 22. Care
should be taken to place the 0.1μF VCC and VDD bypass
capacitor as close to Pins 24 and 25 as possible.
Figure 6 shows the recommended system ground connec-
tions. All analog circuitry grounds should be terminated at
the LTC2351-12 Exposed Pad. The ground return from the
LTC2351-12 to the power supply should be low impedance
for noise-free operation. The Exposed Pad of the 32-pin
QFN package is also internally tied to the ground pads.
The Exposed Pad should be soldered on the PC board to
reduce ground connection inductance. All ground pins
(GND, DGND, OGND) must be connected directly to the
same ground plane under the LTC2351-12.
HARDWARE INTERFACE TO TMS320C54x
The LTC2351-12 is a serial output ADC whose interface
has been designed for high speed buffered serial ports in
fast digital signal processors (DSPs). Figure 7 shows an
example of this interface using a TMS320C54X.
VDD BYPASS,
0.1μF, 0402
OVDD BYPASS,
0.1μF, 0402
VREF BYPASS,
10μF, 0805
VCC BYPASS,
0.1μF, 0402 AND
10μF, 0805
235112 F07
3
30
32
1
2
3-WIRE SERIAL
INTERFACE LINK
OVDD
CONV
SCK
LTC2351-12
SDO
VCC
BFSR
BCLKR
TMS320C54x
BDR
OGND
31
DGND
CONV
0V TO 3V LOGIC SWING
CLK
5V
3V
B11
B10
Figure 6. Recommended Layout
Figure 7. DSP Serial Interface to TMS320C54x
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| LTC2351HUH-12#TRPBF | 6-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC32 |
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