- 您现在的位置：买卖IC网 > PDF目录39417 > LTC2355IMSE-12#TR (LINEAR TECHNOLOGY CORP) 1-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10 PDF资料下载
参数资料
| 型号： | LTC2355IMSE-12#TR |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10 |
| 封装： | PLASTIC, MSOP-10 |
| 文件页数： | 5/16页 |
| 文件大小： | 220K |
| 代理商： | LTC2355IMSE-12#TR |
13
LTC2355-12/LTC2355-14
2355f
Sleep mode and the power consumption drops from
18mW to 13
W. One or more rising edges at SCK wake up
the LTC2355-12/LTC2355-14 for operation. The internal
reference (VREF ) takes 2ms to slew and settle with a 10F
load. Note that, using sleep mode more frequently than
every 2ms, compromises the settled accuracy of the
internal reference. Note that, for slower conversion rates,
the Nap and Sleep modes can be used for substantial
reductions in power consumption.
DIGITAL INTERFACE
The LTC2355-12/LTC2355-14 has a 3-wire SPI-compatible
(Serial Protocol Interface) interface. The SCK and CONV
inputs and SDO output implement this interface. The SCK
and CONV inputs accept swings from 3.3V logic and are
TTL compatible, if the logic swing does not exceed VDD. A
detailed description of the three serial port signals follows.
Conversion Start Input (CONV)
The rising edge of CONV starts a conversion, but
subsequent rising edges at CONV are ignored by the
LTC2355-12/LTC2355-14 until the following 16 SCK rising
edges have occurred. It is necessary to have a minimum
of 16 rising edges of the clock input SCK between rising
edges of CONV. But to obtain maximum conversion speed
(with a 63MHz SCK), it is necessary to allow two more
clock periods between conversions to allow 39ns of acqui-
sition time for the internal ADC sample-and-hold circuit.
With 16 clock periods per conversion, the maximum
conversion rate is limited to 3.5Msps to allow 39ns for
acquisition time. In either case, the output data stream
comes out within the first 16 clock periods to ensure
compatibility with processor serial ports. The duty cycle of
CONV can be arbitrarily chosen to be used as a frame sync
signal for the processor serial port. A simple approach to
generate CONV is to create a pulse that is one SCK wide to
drive the LTC2355-12/LTC2355-14 and then buffer this
signal with the appropriate number of inverters to ensure
the correct delay driving the frame sync input of the
processor serial port. It is good practice to drive the
LTC2355-12/LTC2355-14 CONV input first to avoid digital
noise interference during the sample-to-hold transition
triggered by CONV at the start of conversion. It is also
good practice to keep the width of the low portion of the
CONV signal greater than 15ns to avoid introducing glitches
in the front end of the ADC just before the sample-and-hold
goes into hold mode at the rising edge of CONV.
Minimizing Jitter on the CONV Input
In high speed applications where high amplitude sine
waves above 100kHz are sampled, the CONV signal must
have as little jitter as possible (10ps or less). The square
wave output of a common crystal clock module usually
meets this requirement. The challenge is to generate a
CONV signal from this crystal clock without jitter corrup-
tion from other digital circuits in the system. A clock
divider and any gates in the signal path from the crystal
clock to the CONV input should not share the same
integrated circuit with other parts of the system. As shown
in Figure 6, the SCK and CONV inputs should be driven
first, with digital buffers used to drive the serial port
interface. Also note that the master clock in the DSP may
already be corrupted with jitter, even if it comes directly
from the DSP crystal. Another problem with high speed
processor clocks is that they often use a low cost, low
speed crystal (i.e., 10MHz) to generate a fast, but jittery,
phase-locked-loop system clock (i.e., 40MHz). The jitter in
these PLL-generated high speed clocks can be several
nanoseconds. Note that if you choose to use the frame
sync signal generated by the DSP port, this signal will have
the same jitter of the DSP’s master clock.
APPLICATIO S I FOR ATIO
WU
U
相关PDF资料 |
PDF描述 |
|---|---|
| LTC2355IMSE-14#TR | 1-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10 |
| LTC2355CMSE-14#TR | 1-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10 |
| LTC2356CMSE-12#TR | 1-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10 |
| LTC2356IMSE-12#TR | 1-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10 |
| LTC2356IMSE-14#TR | 1-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2355IMSE-14 | 制造商:Linear Technology 功能描述:IC ADC 14BIT 3 WIRE SPI 3.5MSPS 制造商:Linear Technology 功能描述:IC ADC, 14BIT, 3 WIRE SPI, 3.5MSPS |
| LTC2355IMSE-14#PBF | 功能描述:IC ADC 14BIT 3.5MSPS 10-MSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:microPOWER™ 位数:8 采样率（每秒）:1M 数据接口:串行，SPI? 转换器数目:1 功率耗散（最大）:- 电压电源:模拟和数字 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:24-VFQFN 裸露焊盘 供应商设备封装:24-VQFN 裸露焊盘（4x4） 包装:Digi-Reel® 输入数目和类型:8 个单端，单极 产品目录页面:892 (CN2011-ZH PDF) 其它名称:296-25851-6 |
| LTC2355IMSE-14#TRPBF | 功能描述:IC ADC 14BIT 3.5MSPS 10-MSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
| LTC2356CMSE-12#PBF | 功能描述:IC ADC 12BIT 3.5MSPS 10-MSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
| LTC2356CMSE-12#TRPBF | 功能描述:IC ADC 12BIT 3.5MSPS 10-MSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
发布紧急采购，3分钟左右您将得到回复。