参数资料
型号: LTC2356CMSE-12#TR
厂商: LINEAR TECHNOLOGY CORP
元件分类: ADC
英文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10
封装: PLASTIC, MSOP-10
文件页数: 4/16页
文件大小: 266K
代理商: LTC2356CMSE-12#TR
12
LTC2356-12/LTC2356-14
2356f
Figure 3. The voltage of the external reference must be
higher than the 2.5V output of the internal reference. The
recommended range for an external reference is 2.55V to
VDD. An external reference at 2.55V will see a DC quiescent
load of 0.75mA and as much as 3mA during conversion.
INPUT SPAN VERSUS REFERENCE VOLTAGE
The differential input range has a bipolar
±
voltage
span that equals the difference between the voltage at
the reference buffer output VREF at Pin 3, and the voltage
at the ground (Exposed Pad Ground). The differential input
range of the ADC is
±1.25V when using the internal
reference. The internal ADC is referenced to these two
nodes. This relationship also holds true with an external
reference.
DIFFERENTIAL INPUTS
The LTC2356-12/LTC2356-14 have a unique differential
sample-and-hold circuit that measures input voltages
from ground to VDD. The ADC will always convert the
bipolar difference of AIN+ – AIN–, independent of the
common mode voltage at the inputs. The common mode
rejection holds up at extremely high frequencies, see
Figure 4. The only requirement is that both inputs not go
below ground or exceed VDD. Integral nonlinearity errors
(INL) and differential nonlinearity errors (DNL) are largely
independent of the common mode voltage. However, the
offset error will vary. The change in offset error is typically
less than 0.1% of the common mode voltage.
Figure 5 shows the ideal input/output characteristics for
the LTC2356-12/LTC2356-14. The code transitions occur
midway between successive integer LSB values (i.e.,
0.5LSB, 1.5LSB, 2.5LSB, FS – 1.5LSB). The output code
is straight binary with 1LSB = 2.5V/16384 = 153
V for the
LTC2356-14, and 1LSB = 2.5V/4096 = 610
V for the
LTC2356-12. The LTC2356-14 has 1LSB RMS of random
white noise. Figure 6a shows the LTC1819 converting a
single ended input signal to differential input signals for
optimum THD and SFDR performance as shown in the FFT
plot (Figure 6b).
APPLICATIO S I FOR ATIO
WU
U
Figure 4. CMRR vs Frequency
FREQUENCY (Hz)
100
CMRR
(dB)
0
–20
–40
–60
–80
–100
–120
1k
10k
100k
1M
2356 F04
10M
100M
Figure 5. LTC2356-12/LTC2356-14 Transfer Characteristic
INPUT VOLTAGE (V)
2’S
COMPLEMENT
OUTPUT
CODE
2356 F05
011...111
011...110
011...101
100...000
100...001
100...010
FS – 1LSB
–FS
AIN
LTC2356-14
AIN
+
C1
47pF TO
1000pF
1
R1
51
C3
1
F
C5
0.1
F
5V
–5V
C4
1
F
R5
1k
1.5VCM
R3
499
R4
499
R6
1k
C2
47pF TO
1000pF
R2
51
C6
0.1
F
VIN
1.25VP-P
MAX
2356 F06a
+
U1
1/2 LT1819
+
U2
1/2 LT1819
Figure 6a. The LT1819 Driving the LTC2356-14 Differentially
VREF
2
相关PDF资料
PDF描述
LTC2356IMSE-12#TR 1-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10
LTC2356IMSE-14#TR 1-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10
LTC2356CMSE-14#TR 1-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10
LTC2356CMSE-14#TRPBF 1-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10
LTC2356IMSE-14#TRPBF 1-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10
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