- 您现在的位置：买卖IC网 > PDF目录10664 > LTC2356IMSE-14#PBF (Linear Technology)IC ADC 14BIT 3.5MSPS 10-MSOP PDF资料下载
参数资料
| 型号： | LTC2356IMSE-14#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 7/18页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 3.5MSPS 10-MSOP |
| 标准包装： | 50 |
| 位数： | 14 |
| 采样率（每秒）： | 3.5M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 18mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽）裸露焊盘 |
| 供应商设备封装： | 10-MSOP 裸露焊盘 |
| 包装： | 管件 |
| 输入数目和类型： | 2 个单端，双极；1 个差分，双极 |
| 产品目录页面： | 1349 (CN2011-ZH PDF) |
| 配用： | DC1082A-E-ND - BOARD SAR ADC LTC2356-14 |
LTC2356-12/LTC2356-14
15
2356fb
APPLICATIONS INFORMATION
Note that, using sleep mode more frequently than every
2ms, compromises the settled accuracy of the internal
reference. Note that, for slower conversion rates, the Nap
and Sleep modes can be used for substantial reductions
in power consumption.
DIGITAL INTERFACE
The LTC2356-12/LTC2356-14 has a 3-wire SPI-compatible
(Serial Protocol Interface) interface. The SCK and CONV
inputs and SDO output implement this interface. The SCK
andCONVinputsacceptswingsfrom3.3VlogicandareTTL
compatible,ifthelogicswingdoesnotexceedVDD.Adetailed
description of the three serial port signals follows.
Conversion Start Input (CONV)
The rising edge of CONV starts a conversion, but subse-
quentrisingedgesatCONVareignoredbytheLTC2356-12/
LTC2356-14 until the following 16 SCK rising edges have
occurred. It is necessary to have a minimum of 16 rising
edges of the clock input SCK between rising edges of
CONV. But to obtain maximum conversion speed (with
a 63MHz SCK), it is necessary to allow two more clock
periods between conversions to allow 39ns of acquisition
time for the internal ADC sample-and-hold circuit. With 16
clock periods per conversion, the maximum conversion
rate is limited to 3.5Msps to allow 39ns for acquisition
time. In either case, the output data stream comes out
within the first 16 clock periods to ensure compatibility
with processor serial ports. The duty cycle of CONV can
be arbitrarily chosen to be used as a frame sync signal for
the processor serial port. A simple approach to generate
CONV is to create a pulse that is one SCK wide to drive the
LTC2356-12/LTC2356-14 and then buffer this signal with
the appropriate number of inverters to ensure the cor-
rect delay driving the frame sync input of the processor
serial port. It is good practice to drive the LTC2356-12/
LTC2356-14 CONV input first to avoid digital noise inter-
ference during the sample-to-hold transition triggered by
CONV at the start of conversion. It is also good practice
to keep the width of the low portion of the CONV signal
greater than 15ns to avoid introducing glitches in the front
end of the ADC just before the sample-and-hold goes into
hold mode at the rising edge of CONV.
Minimizing Jitter on the CONV Input
Inhighspeedapplicationswherehighamplitudesinewaves
above 100kHz are sampled, the CONV signal must have
as little jitter as possible (10ps or less). The square wave
output of a common crystal clock module usually meets
this requirement . The challenge is to generate a CONV
signalfromthiscrystalclockwithoutjittercorruptionfrom
other digital circuits in the system. A clock divider and
any gates in the signal path from the crystal clock to the
CONV input should not share the same integrated circuit
with other parts of the system. As shown in Figure 8, the
SCK and CONV inputs should be driven first, with digital
buffers used to drive the serial port interface. Also note
that the master clock in the DSP may already be corrupted
with jitter, even if it comes directly from the DSP crystal.
Another problem with high speed processor clocks is that
they often use a low cost, low speed crystal (i.e., 10MHz)
to generate a fast, but jittery, phase-locked-loop system
clock (i.e., 40MHz). The jitter in these PLL-generated high
speed clocks can be several nanoseconds. Note that if
you choose to use the frame sync signal generated by
the DSP port, this signal will have the same jitter of the
DSP’s master clock.
The Typical Application Figure on page 16 shows a cir-
cuit for level-shifting and squaring the output from an
RF signal generator or other low-jitter source. A single
D-type flip flop is used to generate the CONV signal to
the LTC2356-12/LTC2356-14. Re-timing the master clock
signal eliminates clock jitter introduced by the controlling
device(DSP,FPGA,etc.)Boththeinverterandflipflopmust
be treated as analog components and should be powered
from a clean analog supply.
Serial Clock Input (SCK)
The rising edge of SCK advances the conversion process
and also udpates each bit in the SDO data stream. After
CONV rises, the third rising edge of SCK starts clocking
out the 12/14 data bits with the MSB sent first. A simple
approach is to generate SCK to drive the LTC2356-12/
LTC2356-14 first and then buffer this signal with the
appropriate number of inverters to drive the serial clock
input of the processor serial port. Use the falling edge of
the clock to latch data from the Serial Data Output (SDO)
相关PDF资料 |
PDF描述 |
|---|---|
| VI-B13-MX-F3 | CONVERTER MOD DC/DC 24V 75W |
| AD7894BRZ-10 | IC ADC 14BIT SRL T/H LP 8-SOIC |
| LMX393HAUA+T | IC COMPARATOR GP DUAL 8-UMAX |
| VI-B13-MX-F1 | CONVERTER MOD DC/DC 24V 75W |
| AD9214BRSZ-105 | IC ADC 10BIT 105MSPS 28-SSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2360CS6#TRMPBF | 功能描述:IC ADC 12BIT 100KSPS TSOT23-6 RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:2,500 系列:- 位数:16 采样率（每秒）:15 数据接口:MICROWIRE?，串行，SPI? 转换器数目:1 功率耗散（最大）:480µW 电压电源:单电源 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:38-WFQFN 裸露焊盘 供应商设备封装:38-QFN（5x7） 包装:带卷 (TR) 输入数目和类型:16 个单端，双极；8 个差分，双极 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
| LTC2360CS6#TRPBF | 功能描述:IC ADC 12BIT 100KSPS TSOT23-6 RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:2,500 系列:- 位数:16 采样率（每秒）:15 数据接口:MICROWIRE?，串行，SPI? 转换器数目:1 功率耗散（最大）:480µW 电压电源:单电源 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:38-WFQFN 裸露焊盘 供应商设备封装:38-QFN（5x7） 包装:带卷 (TR) 输入数目和类型:16 个单端，双极；8 个差分，双极 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
| LTC2360CTS8#TRMPBF | 功能描述:IC ADC 12BIT 100KSPS TSOT23-8 RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:2,500 系列:- 位数:16 采样率（每秒）:15 数据接口:MICROWIRE?，串行，SPI? 转换器数目:1 功率耗散（最大）:480µW 电压电源:单电源 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:38-WFQFN 裸露焊盘 供应商设备封装:38-QFN（5x7） 包装:带卷 (TR) 输入数目和类型:16 个单端，双极；8 个差分，双极 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
| LTC2360CTS8#TRPBF | 功能描述:IC ADC 12BIT 100KSPS TSOT23-8 RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:2,500 系列:- 位数:16 采样率（每秒）:15 数据接口:MICROWIRE?，串行，SPI? 转换器数目:1 功率耗散（最大）:480µW 电压电源:单电源 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:38-WFQFN 裸露焊盘 供应商设备封装:38-QFN（5x7） 包装:带卷 (TR) 输入数目和类型:16 个单端，双极；8 个差分，双极 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
| LTC2360HS6#PBF | 制造商:Linear Technology 功能描述:MS-ADC/General Purpose, Cut Tape 12-bit 100ksps SAR ADC in TSOT-6 |
发布紧急采购，3分钟左右您将得到回复。