参数资料
型号: LTC2364IDE-18#TRPBF
厂商: Linear Technology
文件页数: 2/24页
文件大小: 0K
描述: IC ADC 18BIT 250K 1CH 16DFN
产品培训模块: LTC2369- 18-/16-bit Pseudo-Differential SAR ADC Family Overview
标准包装: 2,500
位数: 18
采样率(每秒): 250k
数据接口: 串行,SPI?
转换器数目: 1
功率耗散(最大): 4.25mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-WFDFN 裸露焊盘
供应商设备封装: 16-DFN(4x3)
包装: 带卷 (TR)
输入数目和类型: 1 个伪差分,单极
配用: DC1813A-H-ND - BOARD SAR ADC LTC2364-18
LTC2364-18
10
236418f
OVERVIEW
TheLTC2364-18isalownoise,lowpower,highspeed18-bit
successive approximation register (SAR) ADC. Operating
from a single 2.5V supply, the LTC2364-18 supports a
0V to VREF pseudo-differential unipolar input range with
VREF ranging from 2.5V to 5.1V, making it ideal for high
performance applications which require a wide dynamic
range. The LTC2364-18 achieves ±2.5LSB INL max, no
missing codes at 18 bits and 97dB SNR.
Fast 250ksps throughput with no cycle latency makes
the LTC2364-18 ideally suited for a wide variety of high
speed applications. An internal oscillator sets the con-
version time, easing external timing considerations. The
LTC2364-18 dissipates only 3.4mW at 250ksps, while an
auto power-down feature is provided to further reduce
power dissipation during inactive periods.
CONVERTER OPERATION
The LTC2364-18 operates in two phases. During the ac-
quisition phase, the charge redistribution capacitor D/A
converter (CDAC) is connected to the IN+ and INpins to
sample the pseudo-differential analog input voltage. A ris-
ing edge on the CNV pin initiates a conversion. During the
conversionphase,the18-bitCDACissequencedthrougha
successiveapproximationalgorithm,effectivelycomparing
the sampled input with binary-weighted fractions of the
reference voltage (e.g. VREF/2, VREF/4 … VREF/262144)
using the differential comparator. At the end of conver-
sion, the CDAC output approximates the sampled analog
input. The ADC control logic then prepares the 18-bit
digital output code for serial transfer.
TRANSFER FUNCTION
The LTC2364-18 digitizes the full-scale voltage of REF
into 218 levels, resulting in an LSB size of 19V with
REF = 5V. The ideal transfer function is shown in Figure2.
The output data is in straight binary format.
APPLICATIONS INFORMATION
Figure 2. LTC2364-18 Transfer Function
Figure 3. The Equivalent Circuit for the
Differential Analog Input of the LTC2364-18
ANALOG INPUT
TheanaloginputsoftheLTC2364-18arepseudo-differential
in order to reduce any unwanted signal that is common
to both inputs. The analog inputs can be modeled by the
equivalentcircuitshowninFigure3.Thediodesattheinput
provide ESD protection. In the acquisition phase, each
input sees approximately 45pF (CIN) from the sampling
CDAC in series with 40Ω (RON) from the on-resistance
of the sampling switch. The IN+ input draws a current
spike while charging the CIN capacitor during acquisition.
During conversion, the analog inputs draw only a small
leakage current.
INPUT VOLTAGE (V)
0V
OUTPUT
CODE
236418 F02
111...111
111...110
111...101
111...100
000...001
000...000
000...010
000...011
1
LSB
UNIPOLAR
ZERO
FS – 1LSB
1LSB = FS/262144
RON
40
CIN
45pF
RON
40
REF
CIN
45pF
IN+
IN
BIAS
VOLTAGE
236418 F03
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