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参数资料
| 型号： | LTC2376CMS-18#TRPBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| 封装： | LEAD FREE, PLASTIC, MSOP-16 |
| 文件页数： | 7/24页 |
| 文件大小： | 892K |
| 代理商： | LTC2376CMS-18#TRPBF |
LTC2376-18
15
237618f
TIMING AND CONTROL
CNV Timing
The LTC2376-18 conversion is controlled by CNV. A ris-
ing edge on CNV will start a conversion and power up the
LTC2376-18. Once a conversion has been initiated, it cannot
be restarted until the conversion is complete. For optimum
performance, CNV should be driven by a clean low jitter
signal. Converter status is indicated by the BUSY output
which remains high while the conversion is in progress.
To ensure that no errors occur in the digitized results, any
additional transitions on CNV should occur within 40ns
from the start of the conversion or after the conversion
has been completed. Once the conversion has completed,
the LTC2376-18 powers down and begins acquiring the
input signal.
Acquisition
A proprietary sampling architecture allows the LTC2376-18
to begin acquiring the input signal for the next conver-
sion 527ns after the start of the current conversion. This
extends the acquisition time to 3.460μs, easing settling
requirements and allowing the use of extremely low power
ADC drivers. (Refer to the Timing Diagram.)
Internal Conversion Clock
The LTC2376-18 has an internal clock that is trimmed to
achieve a maximum conversion time of 3μs.
Auto Power-Down
The LTC2376-18 automatically powers down after a con-
version has been completed and powers up once a new
conversion is initiated on the rising edge of CNV. During
power down, data from the last conversion can be clocked
out. To minimize power dissipation during power down,
disable SDO and turn off SCK. The auto power-down feature
will reduce the power dissipation of the LTC2376-18 as
the sampling frequency is reduced. Since power is con-
sumed only during a conversion, the LTC2376-18 remains
powered-down for a larger fraction of the conversion cycle
(tCYC) at lower sample rates, thereby reducing the average
power dissipation which scales with the sampling rate as
shown in Figure 12.
APPLICATIONS INFORMATION
DIGITAL INTERFACE
The LTC2376-18 has a serial digital interface. The flexible
OVDD supply allows the LTC2376-18 to communicate with
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin when
an external clock is applied to the SCK pin if SDO is enabled.
Clocking out the data after the conversion will yield the
best performance. With a shift clock frequency of at least
20MHz, a 250ksps throughput is still achieved. The serial
output data changes state on the rising edge of SCK and
can be captured on the falling edge or next rising edge of
SCK. D17 remains valid till the first rising edge of SCK.
The serial interface on the LTC2376-18 is simple and
straightforward to use. The following sections describe the
operation of the LTC2376-18. Several modes are provided
depending on whether a single or multiple ADCs share the
SPI bus or are daisy chained.
SAMPLING RATE (kHz)
0
50
100
250
200
150
0
POWER
SUPPL
Y
CURRENT
(mA)
1.0
0.8
0.4
0.2
0.6
1.6
1.2
1.4
237618 F12
IVDD
IREF
IOVDD
Figure 12. Power Supply Current of the LTC2376-18
Versus Sampling Rate
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