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参数资料
| 型号： | LTC2393IUK-16#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 7/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT SER/PAR 1M 48-QFN |
| 标准包装： | 2,000 |
| 位数： | 16 |
| 采样率（每秒）： | 1M |
| 数据接口： | 串行，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 175mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN-EP（7x7） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，双极 |
| 配用： | DC1500A-A-ND - BOARD SAR ADC LTC2393-16 |
LTC2393-16
15
239316fa
APPLICATIONS INFORMATION
will finish and then the device will power down. The data
from that conversion can be read after PD = low is applied.
In this mode power consumption drops to a typical value
of 175μW from 140mW. This mode can be used if the
LTC2393-16 is inactive for a long period of time and the
user wants to minimize the power dissipation.
Recovery from Power Shutdown Mode
Once the PD pin is returned to a low level, ending the
power shutdown request, the internal circuitry will begin
to power up. If the internal reference is used, the 2.6kΩ
output impedance with the 1μF bypass capacitor on the
REFIN/REFOUT pins will be the main time constant for
the power-on recovery time. If an external reference is
used, typically allow 5ms for recovery before initiating a
new conversion.
Power Dissipation vs Sampling Frequency
The power dissipation of the LTC2393-16 will decrease
as the sampling frequency is reduced when nap mode
is activated. See Figure 7. In nap mode, a portion of the
circuitry on the LTC2393-16 is turned off after a conversion
has been completed. Increasing the time allowed between
conversions lowers the average power.
TIMING AND CONTROL
The LTC2393-16 conversion is controlled by CNVST. A
falling edge on CNVST will start a conversion. CS and RD
control the digital interface on the LTC2393-16. When
either CS or RD is high, the digital outputs are high
impedance.
CNVST Timing
The LTC2393-16 conversion is controlled by CNVST. A
falling edge on CNVST will start a conversion. Once a
conversion has been initiated, it cannot be restarted until
the conversion is complete. For optimum performance
CNVST should be a clean low jitter signal. Converter status
is indicated by the BUSY output which remains high while
the conversion is in progress. To ensure no errors occur
in the digitized results return the rising edge either within
40ns from the start of the conversion or wait until after
the conversion has been completed. The CNVST timing
needed to take advantage of the reduced power mode of
operation is described in the Nap Mode section.
Internal Conversion Clock
The LTC2393-16 has an internal clock that is trimmed
to achieve a maximum conversion time of 600ns. No
external adjustments are required and with a maximum
acquisition time of 385ns, a throughput performance of
1Msps is guaranteed.
DIGITAL INTERFACE
The LTC2393-16 allows both parallel and serial digital
interfaces. The flexible OVP supply allows the LTC2393-16
to communicate with any digital logic operating between
1.8V and 5V, including 2.5V and 3.3V systems.
Figure 7. Power Dissipation of the LTC2393-16
Decreases with Decreasing Sampling Frequency
SAMPLING FREQUENCY (kHz)
10
POWER
SUPPL
Y
CURRENT
(mA)
20
30
5
15
25
0.1
10
100
1000
239316 G15
0
1
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