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参数资料
| 型号： | LTC2400 |
| 厂商： | Linear Technology Corporation |
| 英文描述： | 24-Bit uPower No Latency ADC in SO-8 |
| 中文描述： | 24位uPower在ADC的无延迟苏- 8 |
| 文件页数： | 16/40页 |
| 文件大小： | 455K |
| 代理商： | LTC2400 |
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16
LTC2400
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground (Pin 4), simplifying the
user interface or isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after V
CC
exceeds 2.2V. The level
applied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and EOC
= 0 once the conversion enters the low power sleep state.
On the falling edge of EOC, the conversion result is loaded
into an internal static shift register. The device remains in
the sleep state until the first rising edge of SCK. Data is
APPLICATIO
S I
N
FOR
ATIO
U
W
U
shifted out the SDO pin on each falling edge of SCK
enabling external circuitry to latch data on the rising edge
of SCK. EOC can be latched on the first rising edge of SCK.
On the 32nd falling edge of SCK, SDO goes HIGH (EOC =
1) indicating a new conversion has begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (HI-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is HI-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
V
CC
F
O
V
REF
SCK
V
IN
SDO
GND
CS
V
REF
0.1V TO V
CC
V
IN
–0.12V
REF
TO 1.12V
REF
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
1
μ
F
2.7V TO 5.5V
LTC2400
SDO
SCK
(EXTERNAL)
CS
DATA OUTPUT
CONVERSION
SLEEP
SLEEP
TEST EOC
TEST EOC
DATA OUTPUT
Hi-Z
Hi-Z
Hi-Z
CONVERSION
2400 F06
MSB
EXR
SIG
BIT 8
BIT 27
BIT 9
BIT 28
BIT 29
BIT 30
EOC
BIT 31
BIT 0
EOC
Hi-Z
V
CC
TEST EOC
Figure 6. External Serial Clock, Reduced Data Output Length
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| LTC2400CS8#TR | 功能描述:IC ADC 24BIT MICROPOWER 8SOIC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
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