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参数资料
| 型号： | LTC2400I |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 24-Bit uPower No Latency ADC in SO-8 |
| 中文描述： | 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO8 |
| 封装： | 0.150 INCH, PLASTIC, SO-8 |
| 文件页数： | 11/40页 |
| 文件大小： | 455K |
| 代理商： | LTC2400I |
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11
LTC2400
APPLICATIO
S I
N
FOR
ATIO
U
W
U
2400 F02
V
CC
+ 0.3V
9/8V
REF
V
REF
1/2V
REF
–0.3V
–1/8V
REF
0
NORMAL
INPUT
RANGE
EXTENDED
INPUT
RANGE
ABSOLUTE
MAXIMUM
INPUT
RANGE
Figure 2. LTC2400 Input Range
For large values of V
REF
this range is limited by the
absolute maximum voltage range of –0.3V to (V
CC
+ 0.3V).
Beyond this range the input ESD protection devices begin
to turn on and the errors due to the input leakage current
increase rapidly.
Input signals applied to V
IN
may extend below ground by
–300mV and above V
CC
by 300mV. In order to limit any
fault current, a resistor of up to 5k may be added in series
with the V
IN
pin without affecting the performance of the
device. In the physical layout, it is important to maintain
the parasitic capacitance of the connection between this
series resistance and the V
IN
pin as low as possible;
therefore, the resistor should be located as close as
practical to the V
IN
pin. The effect of the series resistance
on the converter accuracy can be evaluated from the
curves presented in the Analog Input/Reference Current
section. In addition a series resistor will introduce a
temperature dependent offset error due to the input leak-
age current. A 1nA input leakage current will develop a
1ppm offset error on a 5k resistor if V
REF
= 5V. This error
has a very strong temperature dependency.
Output Data Format
The LTC2400 serial output data stream is 32 bits long. The
first 4 bits represent status information indicating the
sign, input range and conversion state. The next 24 bits are
the conversion result, MSB first. The remaining 4 bits are
sub LSBs beyond the 24-bit level that may be included in
averaging or discarded without loss of resolution.
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0, this
bit is LOW. The sign bit changes state during the zero code.
Bit 28 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0
≤
V
IN
≤
V
REF
, this bit is LOW. If the input is outside the
normal input range, V
IN
> V
REF
or V
IN
< 0, this bit is HIGH.
The function of these bits is summarized in Table 1.
Table 1. LTC2400 Status Bits
Bit 31
EOC
0
0
0
0
Bit 30
DMY
0
0
0
0
Bit 29
SIG
1
1
1/0
0
Bit 28
EXR
1
0
0
1
Input Range
V
IN
> V
REF
0 < V
IN
≤
V
REF
V
IN
= 0
+
/0
–
V
IN
< 0
Bit 27 (fifth output bit) is the most significant bit (MSB).
Bits 27-4 are the 24-bit conversion result MSB first.
Bit 4 is the least significant bit (LSB).
Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may
be included in averaging or discarded without loss of
resolution.
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the first
rising edge of SCK. Bit 30 is shifted out of the device on the
first falling edge of SCK. The final data bit (Bit 0) is shifted
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