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| 型号： | LTC2410CGN#TR |
| 厂商： | Linear Technology |
| 文件页数： | 7/48页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT DIFF INP/REF 16SSOP |
| 标准包装： | 2,500 |
| 位数： | 24 |
| 采样率（每秒）： | 7.5 |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 1mW |
| 电压电源： | 单电源 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，双极 |
| 配用： | DC575A-ND - BOARD DELTA SIGMA ADC LTC2410 |
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LTC2410
15
synchronized with an outside source, the LTC2410 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the FO pin and turns off the internal oscillator. The
frequency fEOSC of the external signal must be at least
2560Hz (1Hz notch frequency) to be detected. The exter-
nal clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and
low periods tHEO and tLEO are observed.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2410 provides better than 110dB
normal mode rejection in a frequency range fEOSC/2560
±4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from fEOSC/2560
is shown in Figure 4.
Whenever an external clock is not present at the FO pin, the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2410
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
Table 3 summarizes the duration of each state and the
achievable output data rate as a function of FO.
SERIAL INTERFACE PINS
The LTC2410 transmits the conversion results and re-
ceives the start of conversion command through a syn-
chronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the
converter status and during the data output state it is used
to read the conversion result.
Table 3. LTC2410 State Duration
State
Operating Mode
Duration
CONVERT
Internal Oscillator
FO = LOW
133ms, Output Data Rate
≤ 7.5 Readings/s
(60Hz Rejection)
FO = HIGH
160ms, Output Data Rate
≤ 6.2 Readings/s
(50Hz Rejection)
External Oscillator
FO = External Oscillator
20510/fEOSCs, Output Data Rate ≤ fEOSC/20510 Readings/s
with Frequency fEOSC kHz
(fEOSC/2560 Rejection)
SLEEP
As Long As CS = HIGH Until CS = LOW and SCK
DATA OUTPUT
Internal Serial Clock
FO = LOW/HIGH
As Long As CS = LOW But Not Longer Than 1.67ms
(Internal Oscillator)
(32 SCK cycles)
FO = External Oscillator with
As Long As CS = LOW But Not Longer Than 256/fEOSCms
Frequency fEOSC kHz
(32 SCK cycles)
External Serial Clock with
As Long As CS = LOW But Not Longer Than 32/fSCKms
Frequency fSCK kHz
(32 SCK cycles)
Figure 4. LTC2410 Normal Mode Rejection When
Using an External Oscillator of Frequency fEOSC
APPLICATIO S I FOR ATIO
WU
U
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC/2560(%)
–12
–8
–4
048
12
NORMAL
MODE
REJECTION
(dB)
2410 F04
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
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