参数资料
型号: LTC2410CGN#TRPBF
厂商: Linear Technology
文件页数: 6/48页
文件大小: 0K
描述: IC ADC 24BIT DIFF INP/REF 16SSOP
标准包装: 2,500
位数: 24
采样率(每秒): 7.5
数据接口: MICROWIRE?,串行,SPI?
转换器数目: 2
功率耗散(最大): 1mW
电压电源: 单电源
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-SSOP
包装: 带卷 (TR)
输入数目和类型: 1 个差分,双极
配用: DC575A-ND - BOARD DELTA SIGMA ADC LTC2410
LTC2410
14
on the rising edge of the 32nd SCK pulse. On the falling
edge of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the IN+ and INpins is maintained
within the – 0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 VREF to
+FS = 0.5 VREF. For differential input voltages greater than
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
Frequency Rejection Selection (FO)
The LTC2410 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and all its
harmonics for 50Hz
±2% or 60Hz ±2%. For 60Hz rejec-
tion, FO should be connected to GND while for 50Hz
rejection the FO pin should be connected to VCC.
The selection of 50Hz or 60Hz rejection can also be made
by driving FO to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
Table 2. LTC2410 Output Data Format
Differential Input Voltage
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 0
VIN*
EOC
DMY
SIG
MSB
VIN* ≥ 0.5 VREF**
0
0110
0
0
0.5 VREF** – 1LSB
0
0101
1
1
0.25 VREF**
0
0101
0
0
0.25 VREF** – 1LSB
0
0100
1
1
0
0100
0
0
–1LSB
0
0011
1
1
– 0.25 VREF**
0
0011
0
0
– 0.25 VREF** – 1LSB
0
0010
1
1
– 0.5 VREF**
0
0010
0
0
VIN* < –0.5 VREF**
0
0001
1
1
*The differential input voltage VIN = IN+ – IN.
**The differential reference voltage VREF = REF+ – REF.
Figure 3. Output Data Timing
APPLICATIO S I FOR ATIO
WU
U
MSB
SIG
“0”
12
3
4
5
26
27
32
BIT 0
BIT 27
BIT 5
LSB24
BIT 28
BIT 29
BIT 30
SDO
SCK
CS
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
2410 F03
Hi-Z
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