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参数资料
| 型号： | LTC2412IGN |
| 厂商： | Linear Technology |
| 文件页数： | 16/36页 |
| 文件大小： | 0K |
| 描述： | IC CONV A/D 24B 2CH DIFF 16-SSOP |
| 标准包装： | 100 |
| 位数： | 24 |
| 采样率（每秒）： | 7.5 |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 1mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SSOP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个差分，双极 |
| 配用： | DC746A-ND - BOARD DELTA SIGMA ADC LTC2412 |
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LTC2412
23
2412f
APPLICATIO S I FOR ATIO
WU
U
Parallel termination near the LTC2412 pin will eliminate
this problem but will increase the driver power dissipation.
A series resistor between 27
and 56 placed near the
driver or near the LTC2412 pin will also eliminate this
problem without additional power dissipation. The actual
resistor value depends upon the trace impedance and
connection topology.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The multiple ground pins used
in this package configuration, as well as the differential
input and reference architecture, reduce substantially the
converter’s sensitivity to ground currents.
Particular attention must be given to the connection of the
FO signal when the LTC2412 is used with an external
conversion clock. This clock is active during the conver-
sion time and the normal mode rejection provided by the
internal digital filter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals may result into DC gain and INL
errors. A normal mode signal of this frequency at the
converter input terminals may result into a DC offset error.
Such perturbations may occur due to asymmetric capaci-
tive coupling between the FO signal trace and the converter
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the FO signal trace and the input/reference sig-
nals. When the FO signal is parallel terminated near the
converter, substantial AC current is flowing in the loop
formed by the FO connection trace, the termination and the
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer-
ence. In this situation, the user must reduce to a minimum
the loop area for the FO signal as well as the loop area for
the differential input and reference connections.
Driving the Input and Reference
The input and reference pins of the LTC2412 converter are
directly connected to a network of sampling capacitors.
Depending upon the relation between the differential input
voltage and the differential reference voltage, these ca-
pacitors are switching between these four pins transfering
small amounts of charge in the process. A simplified
equivalent circuit is shown in Figure 11, where IN+ and IN–
refer to the selected differential channel and the unselected
channel is omitted for simplicity.
VREF+
VIN+
VCC
RSW (TYP)
20k
ILEAK
VCC
ILEAK
VCC
RSW (TYP)
20k
CEQ
18pF
(TYP)
RSW (TYP)
20k
ILEAK
IIN+
VIN–
IIN–
IREF+
IREF–
2412 F11
ILEAK
VCC
ILEAK
SWITCHING FREQUENCY
fSW = 76800Hz INTERNAL OSCILLATOR (FO = LOW OR HIGH)
fSW = 0.5 fEOSC EXTERNAL OSCILLATOR
VREF–
RSW (TYP)
20k
IIN
VV
V
R
IIN
VV
V
R
I REF
VV
V
R
V
VR
I REF
VV
V
R
V
VR
where
AVG
IN
INCM
REFCM
EQ
AVG
IN
INCM
REFCM
EQ
AVG
REF
INCM
REFCM
EQ
IN
REF
EQ
AVG
REF
INCM
REFCM
EQ
IN
REF
EQ
+
+
() = +
() = +
() =
+
() =
+
+
05
15
05
15
05
2
.
::
.
./
V
REF
V
REF
VIN
IN
V
IN
R
M
INTERNAL OSCILLATOR
Hz Notch F
LOW
R
M
INTERNAL OSCILLATOR
Hz Notch F
HIGH
R
f
EXTERNAL OSCILLATOR
REF
REFCM
IN
INCM
EQ
O
EQ
O
EQ
EOSC
=
+
=
==
()
==
()
=
()
+
2
361
60
432
50
0 555 1012
Figure 11. LTC2412 Equivalent Analog Input Circuit
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