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| 型号： | LTC2415IGN#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 5/40页 |
| 文件大小： | 0K |
| 描述： | IC A/D CONV 24BIT MICRPWR 16SSOP |
| 标准包装： | 100 |
| 位数： | 24 |
| 采样率（每秒）： | 15 |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 1mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SSOP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个差分，双极 |
| 产品目录页面： | 1348 (CN2011-ZH PDF) |
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LTC2415/LTC2415-1
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APPLICATIO S I FOR ATIO
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The LTC2415/LTC2415-1 perform a full-scale calibration
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation de-
scribed above. The advantage of continuous calibration is
extreme stability of full-scale readings with respect to time,
supply voltage change and temperature drift.
Unlike the LTC2410 and LTC2413, the LTC2415 and
LTC2415-1 do not perform an offset calibration every
conversion cycle. This enables the LTC2415/LTC2415-1
to double their output rate while maintaining line frequency
rejection. The initial offset of the LTC2415/LTC2415-1 is
within 2mV independent of VREF. Based on the LTC2415/
LTC2415-1 new modulator architecture, the temperature
drift of the offset is less then 0.01ppm/
°C. More informa-
tion on the LTC2415/LTC2415-1 offset is described in the
Offset Accuracy and Drift section of this data sheet.
Power-Up Sequence
The LTC2415/LTC2415-1 automatically enter an internal
reset state when the power supply voltage VCC drops
below approximately 2.2V. This feature guarantees the
integrity of the conversion result and of the serial interface
mode selection. (See the 2-wire I/O sections in the Serial
Interface Timing Modes section.)
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 0.5ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2415/LTC2415-1 start a normal conversion
cycle and follow the succession of states described above.
The first conversion result following POR is accurate
within the specifications of the device if the power supply
voltage is restored within the operating range (2.7V to
5.5V) before the end of the POR time interval.
Reference Voltage Range
These converters accept a truly differential external refer-
ence voltage. The absolute/common mode voltage speci-
fication for the REF+ and REF– pins covers the entire range
from GND to VCC. For correct converter operation, the
REF+ pin must always be more positive than the REF– pin.
The LTC2415/LTC2415-1 can accept a differential refer-
ence voltage from 0.1V to VCC. The converter output noise
is determined by the thermal noise of the front-end cir-
cuits, and as such, its value in nanovolts is nearly constant
with reference voltage. A decrease in reference voltage will
not significantly improve the converter’s effective resolu-
tion. On the other hand, a reduced reference voltage will
improve the converter’s overall INL performance. A re-
duced reference voltage will also improve the converter
performance when operated with an external conversion
clock (external FO signal) at substantially higher output
data rates (see the Output Data Rate section).
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the IN+ and IN– input pins
extending from GND – 0.3V to VCC + 0.3V. Outside
these limits, the ESD protection devices begin to turn on
and the errors due to input leakage current increase
rapidly. Within these limits, the LTC2415/LTC2415-1 con-
vert the bipolar differential input signal, VIN = IN+ – IN–,
from – FS = – 0.5 VREF to +FS = 0.5 VREF where VREF =
REF+ – REF–. Outside this range, the converters indicate
the overrange or the underrange condition using distinct
output codes.
Input signals applied to IN+ and IN– pins may extend by
300mV below ground and above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN+ and IN– pins without affecting the perfor-
mance of the device. In the physical layout, it is important
to maintain the parasitic capacitance of the connection
between these series resistors and the corresponding pins
as low as possible; therefore, the resistors should be
located as close as practical to the pins. The effect of the
series resistance on the converter accuracy can be evalu-
ated from the curves presented in the Input Current/
Reference Current sections. In addition, series resistors
will introduce a temperature dependent offset error due to
the input leakage current. A 1nA input leakage current will
develop a 1ppm offset error on a 5k resistor if VREF = 5V.
This error has a very strong temperature dependency.
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