参数资料
型号: LTC2435CGN#TRPBF
厂商: Linear Technology
文件页数: 18/42页
文件大小: 0K
描述: IC ADC DIFF I/REF 20BIT 16-SSOP
标准包装: 2,500
位数: 20
采样率(每秒): 15
数据接口: MICROWIRE?,串行,SPI?
转换器数目: 2
功率耗散(最大): 1mW
电压电源: 单电源
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-SSOP
包装: 带卷 (TR)
输入数目和类型: 1 个差分,双极
LTC2435/LTC2435-1
25
24351fc
For more information www.linear.com/LTC2435
applicaTions inForMaTion
PRESERVING THE CONVERTER ACCURACY
The LTC2435/LTC2435-1 are designed to reduce as much
as possible conversion result sensitivity to device decou-
pling, PCB layout, anti-aliasing circuits, line frequency
perturbationsandsoon.Nevertheless,inordertopreserve
the extreme accuracy capability of this part, some simple
precautions are desirable.
Digital Signal Levels
The LTC2435/LTC2435-1 digital interface is easy to use.
Its digital inputs (FO, CS and SCK in External SCK mode
of operation) accept standard TTL/CMOS logic levels and
the internal hysteresis receivers can tolerate edge rates
as slow as 100s. However, some considerations are
required to take advantage of the exceptional accuracy
and low supply current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during conversion.
While a digital input signal is in the range 0.5V to
(VCC – 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (FO, CS and SCK
inExternalSCKmodeofoperation)iswithinthisrange,the
LTC2435/LTC2435-1 power supply current may increase
even if the signal in question is at a valid logic level. For
micropower operation, it is recommended to drive all
digital input signals to full CMOS levels [VIL < 0.4V and
VOH > (VCC – 0.4V)].
Duringtheconversionperiod,theundershootand/orover-
shoot of a fast digital signal connected to the LTC2435/
LTC2435-1 pins may severely disturb the analog to digital
conversionprocess.Undershootandovershootcanoccur
because of the impedance mismatch at the converter pin
when the transition time of an external control signal is
less than twice the propagation delay from the driver to
LTC2435/LTC2435-1. For reference, on a regular FR-4
board,signalpropagationvelocityisapproximately183ps/
inch for internal traces and 170ps/inch for surface traces.
Thus, a driver generating a control signal with a minimum
transition time of 1ns must be connected to the converter
pin through a trace shorter than 2.5 inches. This problem
becomes particularly difficult when shared control lines
are used and multiple reflections may occur. The solu-
tion is to carefully terminate all transmission lines close
to their characteristic impedance.
ParallelterminationneartheLTC2435/LTC2435-1pinswill
eliminate this problem but will increase the driver power
dissipation.Aseriesresistorbetween27Ωand56Ωplaced
near the driver or near the LTC2435/LTC2435-1 pins will
also eliminate this problem without additional power dis-
sipation. The actual resistor value depends upon the trace
impedance and connection topology.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The multiple ground pins used
in this package configuration, as well as the differential
input and reference architecture, reduce substantially the
converter’s sensitivity to ground currents.
Particular attention must be given to the connection of
the FO signal when the LTC2435/LTC2435-1 are used
with an external conversion clock. This clock is active
during the conversion time and the normal mode rejec-
tion provided by the internal digital filter is not very high
at this frequency. A normal mode signal of this frequency
at the converter reference terminals may result in DC gain
and INL errors. A normal mode signal of this frequency
at the converter input terminals may result in a DC offset
error. Such perturbations may occur due to asymmetric
capacitive coupling between the FO signal trace and the
converter input and/or reference connection traces. An
immediate solution is to maintain maximum possible
separation between the FO signal trace and the input/ref-
erence signals. When the FO signal is parallel terminated
near the converter, substantial AC current is flowing in the
loop formed by the FO connection trace, the termination
and the ground return path. Thus, perturbation signals
may be inductively coupled into the converter input and/
or reference. In this situation, the user must reduce to a
minimum the loop area for the FO signal as well as the loop
area for the differential input and reference connections.
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