LTC2435/LTC2435-1
13
24351fc
applicaTions inForMaTion
The LTC2435/LTC2435-1 perform a full-scale calibration
every conversion cycle. This calibration is transparent to
theuserandhasnoeffectonthecyclicoperationdescribed
above. The advantage of continuous calibration is extreme
stability of full-scale readings with respect to time, supply
voltage change and temperature drift.
Unlike the LTC2430, the LTC2435 and LTC2435-1 do not
perform an offset calibration every conversion cycle. This
enablestheLTC2435/LTC2435-1todoubletheiroutputrate
whilemaintaininglinefrequencyrejection.Theinitialoffset
of the LTC2435/LTC2435-1 is within 5mV independent of
VREF . Based on the LTC2435/LTC2435-1 new modulator
architecture, the temperature drift of the offset is less than
100nV/°C. More information on the LTC2435/LTC2435-1
offset is described in the Offset Accuracy and Drift section
of this data sheet.
Power-Up Sequence
The LTC2435/LTC2435-1 automatically enter an internal
reset state when the power supply voltage VCC drops
below approximately 2.2V. This feature guarantees the
integrity of the conversion result and of the serial interface
mode selection. (See the 2-wire I/O sections in the Serial
Interface Timing Modes section.)
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signalwithadurationofapproximately1ms.ThePORsignal
clears all internal registers. Following the POR signal, the
LTC2435/LTC2435-1 start a normal conversion cycle and
follow the succession of states described above. The first
conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
Reference Voltage Range
These converters accept a truly differential external
reference voltage. The absolute/common mode voltage
specification for the REF+ and REF– pins covers the entire
rangefromGNDtoVCC.Forcorrectconverteroperation,the
REF+ pin must always be more positive than the REF– pin.
TheLTC2435/LTC2435-1canacceptadifferentialreference
voltage from 0.1V to VCC. The converter output noise is
determined by the thermal noise of the front-end circuits,
and as such, its value is nearly constant with reference
voltage. A decrease in reference voltage will not signifi-
cantly improve the converter’s effective resolution. On the
other hand, a reduced reference voltage will improve the
converter’s overall INL performance. A reduced reference
voltage will also improve the converter performance when
operated with an external conversion clock (external FO
signal) at substantially higher output data rates (see the
Output Data Rate section).
Input Voltage Range
The analog input is truly differential with an absolute/com-
mon mode range for the IN+ and IN– input pins extending
from GND – 0.3V to VCC + 0.3V. Outside these limits, the
ESD protection devices begin to turn on and the errors
due to input leakage current increase rapidly. Within these
limits, the LTC2435/LTC2435-1 convert the bipolar dif-
ferential input signal, VIN = IN+ – IN–, from –FS = –0.5
VREF to + FS = 0.5 VREF where VREF = REF+ – REF–.
Outside this range, the converters indicate the overrange
or the underrange condition using distinct output codes.
Input signals applied to IN+ and IN– pins may extend by
300mV below ground and above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN+ and IN– pins without affecting the perfor-
mance of the device. In the physical layout, it is important
to maintain the parasitic capacitance of the connection
between these series resistors and the corresponding
pins as low as possible; therefore, the resistors should
be located as close as practical to the pins. The effect of
the series resistance on the converter accuracy can be
evaluated from the curves presented in the Input Current/
Reference Current sections. In addition, series resistors
will introduce a temperature dependent offset error due
to the input leakage current. A 1nA input leakage current
will develop a 1ppm offset error on a 5k resistor if VREF =
5V. This error has a very strong temperature dependency.